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FPGA-based DPRAM two-side synchronization system and method

A synchronization system and synchronization module technology, applied in climate sustainability, instruments, electrical digital data processing, etc., can solve problems such as time-consuming, labor-intensive, reading and writing, and poor results, and achieve the effect of simple logic design and high effectiveness

Pending Publication Date: 2022-05-20
SHANGHAI AVIATION ELECTRIC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This creates a problem: For example, if port A writes data into RAM, how can port B perceive and read and write the data in time?
However, this method needs to deal with some special cases: when the periodic write data does not change, or the data is 0, when the query end judges whether it belongs to these special cases, a large number of logic circuits or codes will be added to eliminate this special case , time-consuming and labor-intensive, and the effect is not good

Method used

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  • FPGA-based DPRAM two-side synchronization system and method
  • FPGA-based DPRAM two-side synchronization system and method
  • FPGA-based DPRAM two-side synchronization system and method

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Embodiment Construction

[0016] The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be noted here that the descriptions of these embodiments are used to help the understanding of the present invention, but do not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0017] See figure 1 , the figure shows the port schematic diagram of DPRAM. The DPRAM has an A-side port and a B-side port. The A-side port is used to receive the clock signal Clk_a, the enable signal Wen_a, the address signal Addr_a and the data signal Data_a from the mainboard. The B-side port is used to receive the clock signal Clk_b, the enable signal Wen_b, the address signal Addr_b and the data signal Data_b from the logic module.

[0018] See ...

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Abstract

The invention discloses a DPRAM two-side synchronization system and method based on an FPGA, the system comprises a mainboard and an FPGA daughter board, and the FPGA daughter board is provided with a DPRAM, an A-B synchronization module, a B-A synchronization module and a logic module. The method has the advantages that read-write synchronization of the A port and the B port is almost 100%, logic design is simple, effectiveness is high, and the method is not affected by data invariability and a 0 value.

Description

technical field [0001] The present invention relates to the field of airborne FPGA-based, in particular, a system and method for synchronizing both sides of a DPRAM based on FPGA. Background technique [0002] In the process of airborne equipment research and development, there is often a situation where the main board is connected to a daughter board through PCI, PDI, extended address lines, etc., and the data exchange between the daughter board and the main board is generally in the form of dual-port RAM. In order to achieve the purpose that both the main board and the daughter board can read and write the RAM. [0003] However, DPRAM is just a piece of memory, and the reading and writing of ports on both sides often come from different hardware and APP. This creates a problem: for example, when port A writes data into RAM, how can port B sense and read and write data in time in a timely manner. [0004] At present, most of the design methods are that the B port periodic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
CPCG06F13/1689Y02D10/00
Inventor 张丽魏文正陈利云
Owner SHANGHAI AVIATION ELECTRIC
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