Error correction method for dynamic refreshing of ROM (read only memory) mapping zone in FRGA (field programmable gate array)

Abstract

The invention discloses an error correction method for dynamic refreshing of a ROM (read only memory) mapping zone and a configuration zone in SRAM (static random access memory) type FRGA (field programmable gate array). The method includes: firstly, reading configuration information in configuration files and shielding information in mask word files, determining dynamic refresh prohibited portions and dynamic refresh permitted portions in the configuration information, and classifying the corresponding configuration information of the ROM mapping zone in the configuration zone into dynamic refresh permitted portions; secondly, recording the configuration information into a new configuration file, and identifying whether the configuration information allows to be dynamically refreshed or not in the FPGA embedded logic operating state in the new configuration file; thirdly, using a logic control circuit to read in the configuration information and identification from the new configuration file during dynamic refreshing, and only reading the dynamic refresh permitted configuration information in the configuration zone of the FRGA. Using the method can permit dynamic data refreshing of the ROM mapping zone during repeated data refreshing of the configuration zone, so that accuracy of the data stored in the ROM can be guaranteed.

Description

technical field [0001] The invention relates to the technical field of Field Programmable Logic Gate Array (FPGA), in particular to a static storage (SRAM) type FPGA internal configuration area dynamic refresh error correction method. Background technique [0002] The logic state of the static memory (SRAM) FPGA device (hereinafter referred to as Xilinx FPGA) produced by Xilinx is determined by the data in the configuration area. However, in the actual working process of Xilinx FPGA devices, the data in the configuration area of ​​the FPGA may change due to interference from the external working environment (such as sudden voltage changes, wireless pulse interference, high-energy particle impact, etc.), thereby affecting the normal operation of FPGA embedded logic. [0003] At present, a solution to ensure the correctness of the data in the configuration area is as follows: figure 1 As shown, the external control circuit is used to cyclically reconfigure the configuration d...

AI Technical Summary

Problems solved by technology

This method needs to occupy three times the block RAM resources, and most decision modules also need to occupy additional FPGA logic resources, resulting in a large amount of resource usage, which limits its application in actual engineering practice

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