14 results about "Block ram" patented technology

This invention discloses a method and device for multi-target data storage in a fast interference DRFM system, relating to the field of radio frequency digital signal storage equipment technology. Based on the data read request issued by the DRFM system, the method first outputs the pre-stored data segments in the Block RAM storage space, then sequentially outputs the pre-stored data segments in the FIFO storage space. After the pre-stored data segments in the FIFO storage space are read and output, the remaining data segments are read from the DDR module and output to the FIFO storage space until all data segments of the target data are read. The method uses the FPGA's internal Block RAM and FIFO storage space as a two-level delay buffer for data, and dynamically prioritizes the target data, effectively solving the problems of simultaneous multi-target data storage and fast interference response time in the DRFM system.

The invention discloses a deep learning fusion-based intelligent detection method and system for bar collision of a car stop, and belongs to the technical field of safety monitoring of intelligent traffic facilities. The method comprises the steps of collecting an original time sequence data stream of a car stop rod in real time, carrying out preprocessing and feature extraction on the original time sequence data stream, constructing a multi-dimensional feature time sequence, inputting the multi-dimensional feature time sequence into a pre-trained deep learning behavior recognition model, calculating a classification probability and a feature embedding vector, and carrying out feature extraction on the classification probability and the feature embedding vector. And performing real-time similarity comparison on the abnormal confidence coefficient and a template in a reference behavior feature library, generating an abnormal confidence coefficient score according to a self-adaptive dynamic threshold value strategy, and if the abnormal confidence coefficient score continuously exceeds a self-adaptive dynamic threshold value and accords with a preset collision behavior time sequence mode, judging that a rod collision behavior occurs, and starting a linkage evidence obtaining and alarm process. The problems that a traditional scheme is high in false alarm rate and poor in environmental adaptability are solved, and accurate and intelligent detection and automatic evidence obtaining of the rod collision behavior are achieved.

The invention belongs to the technical field of digital circuit design, and particularly relates to a TCAM (ternary content addressable memory)-based quick matching search method, which comprises the following steps of: combining a block RAM (random access memory) and a distributed RAM to construct a TCAM; according to the length of the search word, dividing the search word into a plurality of search sub-words according to bits; according to the length of a search sub-word, inputting the search sub-word into a sub-block RAM or a sub-distributed RAM, processing results of a plurality of sub-RAMs, inputting the processed results into an encoder, and outputting a matching address by the encoder; and searching a corresponding operation in the RAM of the matched address and executing the operation. Compared with the prior art, the method has the advantages that the Block RAM (BRAM) and the LUTRAM in the FPGA are comprehensively utilized to optimize the method for dividing the search words, the BRAM and the LUTRAM are flexibly combined, the optimized composite TCAM (OC-TCAM) which is closer to or even fits the number of bits of the search words is achieved, and consumption of storage resources is greatly reduced.

The invention provides a method for supporting large-capacity SDH virtual cascade grouping on an FPGA chip, and belongs to the technical field of optical transmission. The method comprises the following steps of: creating a shared cache region on an FPGA (Field Programmable Gate Array), and sharing the shared cache region for all virtual cascade groups; the shared cache region comprises a blocky RAM (Random Access Memory) cache region and an RAM management unit; the block RAM cache region is obtained by all block RAM sets used for processing virtual cascade group data reduction on the FPGA chip; and the RAM management unit dynamically applies for a cache region for the virtual cascade group according to the number of members of the virtual cascade group, and is provided with a logic initialization module, a management FIFO queue and a resource use counter. The method provided by the invention can support the processing of a larger number of virtual cascade packets, and can also support the processing of a larger access bandwidth at the same time, thereby avoiding the problem that hardware can only be expanded due to excessive virtual cascade packets of access signals in a practical application scene.

This paper presents an efficient hash core scheduling method and system for the SPHINCS+ signature algorithm, belonging to the field of information security technology. By pre-computing a fixed prefix shared by multiple hash functions in SPHINCS+, one SHA-256 compression function calculation is saved for each related hash function call, resulting in significant cumulative savings in computation and energy consumption. By merging multiple independent FORS trees into a logical whole and employing a depth-first traversal strategy with grouped rounds, a sufficient number of independent hash tasks are always available for the pipeline hash core to process, thus eliminating pipeline stalls. By grouping WOTS+ instances, the number of chains to be computed in each group matches the pipeline depth, ensuring uninterrupted continuous operation of the pipeline core when processing WOTS+ chain values, greatly improving the throughput of the computation stage. The use of a depth-first computation strategy and a dual-port RAM storage design significantly saves valuable on-chip Block RAM resources, enabling SPHINCS+ to be implemented on resource-constrained embedded devices.

The application discloses a kind of periodic characteristic magnetic field signal real-time filtering system and method based on FPGA, for replacing the iteration post-processing of host computer offline software.System includes data acquisition interface and FPGA master unit, and pipeline processing module is constructed inside FPGA: power frequency suppression, low-pass filtering and Savitzky-Golay shape smoothing are carried out to input digital signal;Based on smoothed signal, differential absolute value is constructed, and synchronous trigger pulse is generated through adaptive threshold and refractory mechanism;Under trigger reference, single-cycle template is maintained using dual-port Block RAM, and displacement recursive weighting is used to realize recursive synchronous average and output filtered enhanced magnetic field waveform.The scheme can effectively suppress non-periodic baseline drift and reduce storage and computing overhead, and is suitable for online real-time magnetic field signal processing of low-cost FPGA.

The invention discloses a satellite communication load phased array FPGA reliability enhancement system and method. The system comprises a phased array FPGA, a processor, a first FPGA and a second FPGA, wherein the first FPGA and the second FPGA are divided by the phased array FPGA; the first FPGA comprises a main FPGA and a standby FPGA; when the processor detects that the working parameters of the main FPGA are abnormal, the standby FPGA is started to execute core communication processing; the processor carries out triple-modular redundancy processing on the program stored in the FLASH; the processor monitors working parameters of the second FPGA; and the first FPGA, the second FPGA, the configuration RAM, the block RAM, the DSP, the SERDES, the clock IO and the like are used for carrying out single event effect resisting processing according to the characteristics of the phased array load. According to the scheme, the radiation resistance of the satellite communication load phased array FPGA can be improved, reliable loading of an FPGA program is realized, the communication reliability is enhanced, and the implementation complexity is reduced.

The utility model belongs to the technical field of avionics, and particularly relates to an acquisition device of a low-cost light small recorder. According to the acquisition device, a Microblaze soft core of an FPGA chip is used as a core CPU processor of the acquisition device; fPGA resources are used for building a data acquisition module, a Debug module, a Local Memory local memory, a timer module, a watchdog module, a reset module, a USB module, a hard disk management module, an AXI bridge, a register interaction module, a Block RAM module 0, a UART serial port module, a Flash module, an XADC module, a DDR module and a Block RAM module 1, different data acquisition requirements can be met, and the requirements of low cost, small size, low power consumption and high reliability can be met.

The invention discloses a Block RAM (Random Access Memory) process mapping method. In the target FPGA design, obtaining a target memory to be processed and current attribute information; if the non-standard memory template register transfer level design is determined, obtaining current random access memory layout netlist information, a current read-write port and a current layout netlist; and querying the current layout netlist through a layout netlist traversal search method to obtain target memory query description information, matching the target memory query description information with a memory splitting processing method library, and obtaining a target standard splitting processing memory according to a matched memory splitting processing mode so as to realize Block RAM process mapping. The problems that the workload is large due to RTL rewriting and the product performance is poor due to mapping to non-special physical storage resources are solved, and accurate process mapping of the split memory is improved.

The invention discloses a star target extraction FPGA parallel computing method suitable for a star sensor, and relates to the field of photoelectric imaging, and the method comprises the following steps: firstly, preprocessing a star map through high-pass filtering and Robinson Guard filtering; the method comprises the following steps of: realizing row delay of pixel data by utilizing FIFO (First In First Out) in an FPGA (Field Programmable Gate Array), improving a target clustering mode from row-by-row scanning to column-by-column scanning propulsion, and allocating a BRAM (Border Random Access Memory) and a DRAM (Dynamic Random Access Memory) to construct a clustering data storage Then, carrying out connectivity search on inter-column clustering data by adopting a heap structure, and synchronously calculating characteristic parameters such as a centroid coordinate, a gray scale and the like of a target in a clustering process; and finally, according to the morphological features of the targets, removing false targets, and sorting and outputting the extraction results according to gray levels. According to the invention, parallel computing of image processing and target extraction is realized by using fewer FPGA resources, and target information can be output while image acquisition is completed, so that the bottleneck of computing speed caused by large-size star map processing is effectively solved, and the output frame rate of the star sensor is improved.

The invention discloses a data transmission implementation method, device and equipment applied to multiple subsystems and a medium, and relates to the technical field of data transmission, and the method comprises the following steps: according to the number of subsystems, establishing an independent FIFO cache space for uplink data of each subsystem, and establishing at least four FIFO cache spaces for downlink data of each subsystem; performing data packet integrity verification based on LVDS time sequence association according to the actual data frame interval time of the sending data of each subsystem; transmitting the uplink data and the downlink data through the FIFO cache space corresponding to the uplink data and the downlink data of each subsystem based on the integrity verification result; based on FPGA hardware time sequence verification logic, data verification delay is reduced to 50-400 ns from existing 10-20 ms, meanwhile, a physically independent Block RAM FIFO is configured for each subsystem, absolute independence of data is achieved through hardware resource isolation, and data conflicts are avoided.

The invention discloses an asynchronous dual-port memory and a real-time digital phase shifter system, the asynchronous dual-port memory is introduced into the real-time digital phase shifter system, and the asynchronous dual-port memory comprises a memory access time slot used for dynamically distributing a dual-port block RAM according to a data read-write task request, the controller is used for receiving a Gray code counter and issuing a stepping instruction of the Gray code counter and a cross-domain control instruction of the clock domain cross module; the Gray code counter is used for receiving a stepping instruction of the controller and outputting a Gray code address to the dual-port block RAM; the clock domain cross module is used for receiving a cross-domain control instruction and providing a synchronous access signal for the dual-port block RAM; and executing asynchronous read-write operation according to the Gray code address, the synchronous access signal and the allocated memory access time slot, and storing a dual-port block RAM of a phase and power data pair of the asynchronous read-write operation. The method has the characteristics of high data access efficiency, real-time performance and high precision.

The invention discloses a timer based on an FPGA (Field Programmable Gate Array), which comprises a timeout task insertion module, a timeout task detection module and a timing module, and is characterized in that the timeout task insertion module is used for receiving timeout task information and timeout time, calculating a target time slice of task insertion according to the timeout time, and sending the target time slice to the timeout task detection module; updating the number of tasks in a corresponding time slice in a time slice storage space on the Block RAM; calculating a storage address of the task information, and storing the overtime task information at a corresponding position of a task information storage space on the DDR; the overtime task detection module is used for detecting the number of tasks stored in the time slice pointed by the index according to the time slice index maintained by the timing module, extracting the corresponding task information and resetting the number of tasks corresponding to the current time slice; and the timing module is used for timing by adopting an upward counting mode and maintaining a time slice index. According to the invention, efficient task scheduling and execution processes can be realized.

The application relates to the technical field of image data processing, in particular to an image data transmission method and device based on FPGA and computer equipment, which can solve the problem of waste of block RAM resources caused by insufficient utilization of the width of the block RAM in the storage mode of separately buffering image data of each channel in each block RAM. The method comprises the following steps: determining the number of block RAMs based on the channel width and the number of channels of each channel; in each channel, splicing image data received in a continuous preset number of moments to obtain spliced image data; in the preset number of moments, spliced image data of all channels is sequentially written into different addresses of corresponding block RAMs, wherein the image data of the same spliced image data is written into the same address of the same block RAM; after one line of image data is written into the block RAM, the image data is sequentially read from the same address of all block RAMs.