SRAM (static random access memory) type FPGA SEU (field programmable gate array single event upset) operation fixing method

Abstract

The invention discloses an SRAM (static random access memory) type FPGA SEU (field programmable gate array single event upset) operation fixing method, belonging to the technical field of configuration of SRAM type FPGAs. The method comprises the following steps: 1) after an SRAM type FPGA is electrified, a configuration management FPGA is used for carrying out whole configuration on the SRAM type FPGA; 2) the configuration management FPGA reads a configuration bit stream file, detects the bit stream file and carrying out the follow steps: when a frame write-in command FDRI in the bit stream file is detected, an incidental frame word number in the FDRI is replaced with a logic and interconnection frame word number; when content configuration dada Block RAM is detected, the Block RAM is replaced with a no-operation command; when a register resetting command GRESTORE is detected, the GRESTORE is replaced with a no-operation command; when I / O start command STARTUP is detected, the STARTUP is replaced with a no-operation command; 3) the bit stream file which is subjected to the process of the step 2) is written into the SRAM type FPGA; and 4) the step 2) and the step 3) are repeated until the SRAM type FPGA stops working. The method is suitable for SRAM type FPGA SEU operation fixation.

Description

technical field [0001] The invention relates to the technical field of SRAM FPGA configuration, in particular to a method for repairing an SRAM FPGA SEU during operation. Background technique [0002] Virtex-5 series FPGA is a new FPGA based on SRAM technology launched by Xilinx. It has high integration and strong logic function, and is widely used in modern digital system design. The logic function configuration of Virtex-5FPGA is realized by the data in its SRAM type configuration area, [0003] The SRAM attribute determines that the data in the configuration area will be lost after power-off, so the configuration data must be saved in an external non-volatile memory and reconfigured after the FPGA is powered on. [0004] In aerospace applications, the single event flip SEU in the SRAM FPGA configuration area caused by space high-energy particle bombardment may cause FPGA logic errors. The single event flip in the FPGA configuration area must be repaired to ensure the nor...

AI Technical Summary

Problems solved by technology

In addition to the relatively complex logic, the biggest disadvantage of this method is that both the .msk and .rbb files have the same size as the original configuration file .bit, resulting in three times the storage space occupied; and due to the readback of the configuration area It takes a long time and cannot reach the real-time performance required for in-progress repairs

Therefore, the above "readback-comparison-writeback" method is not practical

Images