16 results about "Block random access memory" patented technology

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention discloses a real-time image super-resolution processing system and method based on an FPGA, and relates to the technical field of image processing, and the system comprises at least one convolution module and a pixel alignment and rearrangement module. The convolution module obtains convolution input pixel data, edge pixel filling processing and caching processing are carried out on the convolution input pixel data to obtain a pixel matrix, convolution processing is carried out according to the pixel matrix to obtain convolution output pixel data, and data caching is carried out based on the block random access memory in the processing process of the convolution module; the pixel alignment and rearrangement module obtains to-be-aligned pixel data, alignment processing and rearrangement processing are carried out on the to-be-aligned pixel data, processed target output pixel data are obtained, and the to-be-aligned pixel data is convolution output pixel data output by the last convolution module; the resolution of the target output pixel data is higher than that of the to-be-processed image frame. In this way, the efficiency of image super-resolution processing is improved, and the real-time requirement is met.

The invention discloses a circuit device for quickly initializing a block random access memory (BRAM) and a working method, which can improve the initialization speed of the BRAM, greatly save the initialization time and have high resource utilization rate. The BRAM circuit comprises a BRAM circuit, a data pre-classification module and an initialization controller, the BRAM circuits exist in the FPGA in the form of column circuits, and the column serial numbers of the BRAM column circuits in each row are consistent; a data pre-classification module finds a BRAM initial value in a bit stream file, initial value data of BRAM columns in each row of the FPGA are forwarded to an initialization controller in a data frame mode, and one frame of initialization value is forwarded in each row; and the initialization controller writes a plurality of frames of initialization values into the BRAM column circuit of each row in parallel in a clock period, and initializes the BRAM circuits of all rows of the FPGA.

The application discloses a multi-device timing control method, which performs timing control on each to-be-executed instruction, and executes each to-be-executed instruction based on an execution time sequence, so that the instruction sending precision reaches a sub-millisecond level, and the high real-time task requirement is met. In addition, the address jump function is used for realizing dynamic instruction adjustment, adapting to various task scenes, and improving the flexibility of multi-device timing control. In addition, the block random access memory and the nonvolatile memory support a plurality of large-scale instruction sets, reduce rewriting overhead, and can reduce hardware upgrade cost, extend functions through software configuration, and improve system reusability.

The invention discloses a CNN (Convolutional Neural Network) data access method for an FPGA (Field Programmable Gate Array), which belongs to the technical field of CNN data access, and comprises the following steps: 1, inputting feature maps, and fragmenting the feature maps, each fragment comprising a plurality of feature maps, 2, determining the number of BRAMs (Block Random Access Memory) in a CNN, and optimizing the BRAMs, 3, selecting a first feature map group, and 4, selecting a second feature map group, s3, splicing all the feature pixel data in the first feature image group, 4, processing the feature image group by using the same method as S3 until the feature pixel data of all the feature image groups are spliced, and 5, interweaving all the spliced feature pixel data according to the sequence of fragmentation, the CNN data access method for the FPGA platform is designed by adopting the method, the bandwidth can be utilized to the maximum when high parallel processing is carried out, the problem of read address conflict is solved by using the optimized BRAM, and the read of interleaved data can be completed in one clock period.

The invention provides a layout method and device for optimizing a time sequence by limiting network weight variation, and the method comprises the steps: obtaining a layout result of an FPGA (Field Programmable Gate Array), the layout result comprises layout positions and connection relationships of a plurality of units, calculating a time sequence margin of a plurality of networks of a target unit according to the layout result, determining a first time sequence margin corresponding to the critical path of the target unit; the target unit comprises a digital signal processing unit and a block random access memory unit, and the critical path is obtained according to the size of a line network time sequence margin; and screening the plurality of wire nets of the target unit, and enhancing the weight of the wire nets through a wire net weight formula according to the size of the time sequence margin of the wire nets.

The invention relates to a video frame component oscillogram real-time generation and superposition display method and system. The method comprises the steps that video signal input and component extraction are carried out, double frames are alternately cached to a PSRAM, inter-row burst reading is initiated in the column direction, and N columns of data in one row are read in each burst mode; a plurality of block random access memories in the FPGA chip are utilized to construct a multi-column parallel statistical unit, a histogram array is constructed, and parallel statistics is carried out on M columns of data at the same time; after the statistics is completed, alternately writing the statistical results of each column into two special statistical result buffer areas in the external PSRAM; according to a user output display demand, suddenly reading a statistical value of a corresponding column from a statistical result buffer area of an external PSRAM according to the demand, generating an oscillogram in the FPGA chip, superposing the oscillogram and an original video signal, and outputting the superposed oscillogram and the original video signal; compared with the prior art, the method has the core advantages of efficient storage access, high parallel processing, low delay superposition, resource optimization and utilization and the like.

The invention relates to a general verification method, system and device for a storage controller and a storage medium, and relates to the technical field of prototype verification. The method is based on an FPGA (Field Programmable Gate Array) and an external DDR (Double Data Rate), and comprises the following steps: constructing a softmodel in the FPGA, constructing a BRAM (Block Random Access Memory) activation line cache pool in the FPGA, and setting the capacity configuration of the BRAM activation line cache pool according to a storage controller; calling an MIG core according to the model of the FPGA, and generating an MIG core IP according to the external DDR; a storage controller read-write verification instruction is sent by the storage controller through softmodel, and the BRAM is called to activate the line cache pool and the external DDR to execute the storage controller read-write verification instruction through the MIG core IP. The technical effect of the application is that prototype verification of the storage controller is better realized.

The invention provides a memory address access control system for fast number-theory transformation. The system comprises an initial address generation module configured to generate initial address data; the address mapping module is configured to set address mapping for the initial address data and generate actual address data; the block random access memories are used for storing data required by the NTT operation, and the data required by the NTT operation correspond to the actual address data; and the butterfly operation modules are configured to perform data reading of a plurality of stages on the data required by the NTT operation stored in the block random access memory in a single parallel or multi-parallel mode according to the actual address data, and perform butterfly operation on the data required by the NTT operation read in each stage. According to the invention, the address mapping unit is introduced to realize equivalent memory redivision, so that low-complexity control logic is realized under the condition of ensuring flexibility and storage constraints.

The invention provides a block random access memory data initialization method and system in an FPGA (Field Programmable Gate Array). The method comprises the following steps that: an upper computer is connected with an initialization controller of a block random access memory in an FPGA (Field Programmable Gate Array) through an enable signal line and a data signal line; when the enable signal line is pulled up at the falling edge of the clock, initialization is started; the data signal line starts serial transmission of the address and data of the target block random access memory in the next clock period after the enable signal is valid; the initialization controller analyzes the address and the data and writes the address and the data into a storage unit of a corresponding block random access memory; and after initialization is completed, the enable signal line is pulled down. Some embodiments of the present disclosure aim to solve the problems in the prior art that protocols are bloated, data lines are used too many, and dynamic initialization cannot be performed.

A system and method for testing Error Correcting Code (“ECC”) function of Field Programmable Gate Array (“FPGA”) on-chip block random access memory (“BRAM”) includes control modules, at least two BRAMs with ECC function and sequentially connected to form a ring, and parity bit comparison modules corresponding to each BRAM. Each parity bit comparison module is connected to its corresponding BRAM and the next adjacent BRAM. The control module is used to send data read and write test instructions to each BRAM. Each BRAM is used to read test data sequentially, write test data into next adjacent BRAM whenever the test data is read, and send the first parity bit generated during reading to the corresponding parity bit comparison module. Each parity bit comparison module is used to compare the first and second parity bits, where the second parity bit is generated during the writing of test data. The embodiments of the present invention reduce the required test stimuli and the interactions with upper computer ports, which enhances the test efficiency.

The present disclosure provides a method and system for initializing block random access memory data in FPGA. The method comprises: connecting an upper computer to an initialization controller of a block random access memory in FPGA through an enable signal line and a data signal line; pulling the enable signal line high at the falling edge of a clock to indicate the start of initialization; starting to serially transmit the address and data of the target block random access memory on the data signal line at the next clock cycle after the enable signal is valid; the initialization controller parses the address and data and writes them into the storage unit of the corresponding block random access memory; and pulling the enable signal line low after the initialization is completed. Some embodiments of the present disclosure aim to solve the problems of bulky protocol, excessive use of data lines and inability to dynamically initialize in the prior art.

The invention relates to a multi-channel synchronous acquisition device based on an FPGA (Field Programmable Gate Array), which comprises a digital signal acquisition module and an analog signal acquisition module, and is characterized in that the digital signal acquisition module comprises a digital signal input end, a digital signal delay unit and a digital signal output end which are connected in sequence; the analog signal acquisition module comprises an analog signal input end, a first-stage multi-channel extractor, a second-stage multi-channel extractor, a selector and an analog signal output end, and the analog signal input end, the first-stage multi-channel extractor, the selector and the analog signal output end are connected in sequence; the first-stage multi-channel extractor, the second-stage multi-channel extractor and the selector are connected in sequence; the digital signal delay unit adopts a block random access memory in an FPGA (Field Programmable Gate Array); and the primary multichannel extractor and the secondary multichannel extractor both adopt DSP (Digital Signal Processor) units in the FPGA. Compared with the prior art, the method has the advantages that the synchronization characteristic of all channels of digital signals and analog signals can be ensured, and the like.

The invention provides an FPGA (Field Programmable Gate Array) BRAM (Bipolar Random Access Memory) reliability design method for resisting single event upset, which comprises the following steps of: setting a port control module transa and a port control module transb, controlling one of two data read-write ports of an FPGA BRAM by using the port control module transa, and controlling the other one of the two data read-write ports of the FPGA BRAM by using the port control module transb; the data read-write port controlled by the port control module transa is used for data read-write, and the data read-write port controlled by the port control module transb is used as a refreshing port and is used for monitoring read-write operation of the data read-write port and automatically refreshing data when the data read-write port does not read or write. The method is relatively simple to control and realize, occupies less resources, and can realize high-reliability transmission of user data. And moreover, the firmware operation abnormal risk caused by single event upset can be reduced, and the radiation resistance and reliability of the solid memory equipment can be effectively improved.

This invention discloses a hyperspectral image band sampling method and system, mainly addressing the problems of complex search strategies and long matrix calculation times in existing band selection algorithms, resulting in poor real-time performance and low efficiency. The solution includes: using an FPGA to set an n-order linear feedback shift register, a feedback polynomial, and a seed value; calculating the first band index value for band sampling based on the number of input sampling bands; generating a series of uniformly sampled band index values ​​using the FPGA based on the first band index value; generating the address for storing the hyperspectral image in external space through linear mapping based on the uniformly sampled band index values; reading a portion of the hyperspectral image bands according to this address and storing them in the FPGA's block random access memory. This invention can reduce the complexity of band dimensionality reduction and computational load while preserving the original image information, greatly shortening the real-time sampling time for hyperspectral image bands and improving sampling efficiency. It can be used for efficient real-time hyperspectral information processing on hardware-restricted platforms such as spaceborne and airborne platforms.

The invention discloses a multi-device timing control method, and the method carries out the timing control of each to-be-executed instruction, and executes each to-be-executed instruction based on an execution time sequence, guarantees the instruction sending precision to reach a sub-millisecond level, and meets the high-real-time task demands. Besides, dynamic instruction adjustment is realized through an address jump function, so that the method adapts to variable task scenes, and the flexibility of multi-device timing control is improved; in addition, the block random access memory and the nonvolatile memory support multiple groups of large-scale instruction sets, so that the rewriting overhead is reduced, the hardware upgrading cost can be reduced, functions can be expanded through software configuration, and the system reusability is improved.