6 results about "Block random access memory" patented technology

The application discloses a multi-device timing control method, which performs timing control on each to-be-executed instruction, and executes each to-be-executed instruction based on an execution time sequence, so that the instruction sending precision reaches a sub-millisecond level, and the high real-time task requirement is met. In addition, the address jump function is used for realizing dynamic instruction adjustment, adapting to various task scenes, and improving the flexibility of multi-device timing control. In addition, the block random access memory and the nonvolatile memory support a plurality of large-scale instruction sets, reduce rewriting overhead, and can reduce hardware upgrade cost, extend functions through software configuration, and improve system reusability.

The invention relates to a video frame component oscillogram real-time generation and superposition display method and system. The method comprises the steps that video signal input and component extraction are carried out, double frames are alternately cached to a PSRAM, inter-row burst reading is initiated in the column direction, and N columns of data in one row are read in each burst mode; a plurality of block random access memories in the FPGA chip are utilized to construct a multi-column parallel statistical unit, a histogram array is constructed, and parallel statistics is carried out on M columns of data at the same time; after the statistics is completed, alternately writing the statistical results of each column into two special statistical result buffer areas in the external PSRAM; according to a user output display demand, suddenly reading a statistical value of a corresponding column from a statistical result buffer area of an external PSRAM according to the demand, generating an oscillogram in the FPGA chip, superposing the oscillogram and an original video signal, and outputting the superposed oscillogram and the original video signal; compared with the prior art, the method has the core advantages of efficient storage access, high parallel processing, low delay superposition, resource optimization and utilization and the like.

The invention relates to a general verification method, system and device for a storage controller and a storage medium, and relates to the technical field of prototype verification. The method is based on an FPGA (Field Programmable Gate Array) and an external DDR (Double Data Rate), and comprises the following steps: constructing a softmodel in the FPGA, constructing a BRAM (Block Random Access Memory) activation line cache pool in the FPGA, and setting the capacity configuration of the BRAM activation line cache pool according to a storage controller; calling an MIG core according to the model of the FPGA, and generating an MIG core IP according to the external DDR; a storage controller read-write verification instruction is sent by the storage controller through softmodel, and the BRAM is called to activate the line cache pool and the external DDR to execute the storage controller read-write verification instruction through the MIG core IP. The technical effect of the application is that prototype verification of the storage controller is better realized.

The invention provides a block random access memory data initialization method and system in an FPGA (Field Programmable Gate Array). The method comprises the following steps that: an upper computer is connected with an initialization controller of a block random access memory in an FPGA (Field Programmable Gate Array) through an enable signal line and a data signal line; when the enable signal line is pulled up at the falling edge of the clock, initialization is started; the data signal line starts serial transmission of the address and data of the target block random access memory in the next clock period after the enable signal is valid; the initialization controller analyzes the address and the data and writes the address and the data into a storage unit of a corresponding block random access memory; and after initialization is completed, the enable signal line is pulled down. Some embodiments of the present disclosure aim to solve the problems in the prior art that protocols are bloated, data lines are used too many, and dynamic initialization cannot be performed.

The present disclosure provides a method and system for initializing block random access memory data in FPGA. The method comprises: connecting an upper computer to an initialization controller of a block random access memory in FPGA through an enable signal line and a data signal line; pulling the enable signal line high at the falling edge of a clock to indicate the start of initialization; starting to serially transmit the address and data of the target block random access memory on the data signal line at the next clock cycle after the enable signal is valid; the initialization controller parses the address and data and writes them into the storage unit of the corresponding block random access memory; and pulling the enable signal line low after the initialization is completed. Some embodiments of the present disclosure aim to solve the problems of bulky protocol, excessive use of data lines and inability to dynamically initialize in the prior art.

This invention discloses a hyperspectral image band sampling method and system, mainly addressing the problems of complex search strategies and long matrix calculation times in existing band selection algorithms, resulting in poor real-time performance and low efficiency. The solution includes: using an FPGA to set an n-order linear feedback shift register, a feedback polynomial, and a seed value; calculating the first band index value for band sampling based on the number of input sampling bands; generating a series of uniformly sampled band index values ​​using the FPGA based on the first band index value; generating the address for storing the hyperspectral image in external space through linear mapping based on the uniformly sampled band index values; reading a portion of the hyperspectral image bands according to this address and storing them in the FPGA's block random access memory. This invention can reduce the complexity of band dimensionality reduction and computational load while preserving the original image information, greatly shortening the real-time sampling time for hyperspectral image bands and improving sampling efficiency. It can be used for efficient real-time hyperspectral information processing on hardware-restricted platforms such as spaceborne and airborne platforms.