Screening and testing method of FPGA embedded multiplier

Abstract

The invention relates to a method for testing the performance of an FPGA embedded multiplier. The method comprises the following steps of 1 embedded multiplier IP core function deign, 2 pseudorandom sequence test vector design, 3 RTL-level code emulation, 4, testing result analysis circuit design and 5 module copying and output logic design. According to the Screening and testing method of the FPGA embedded multiplier, a testing method based on a BIST is adopted, and the defects that the ATE testing expense is high, and the testing technical difficulty is large are overcome. Meanwhile, a pseudorandom sequence is adopted as excitory input, the testing time is shortened, and the testing efficiency is improved. According to the method, the programmable characteristic of an FPGA chip and richchannel resources and a block random access memory (BRAM) in the chip are fully utilized. The method is simple in implementation step and high in transportability and has certain engineering application value.

Description

technical field [0001] The invention relates to a screening and testing method for an FPGA embedded multiplier, belonging to the technical field of integrated circuits. Background technique [0002] With the development of technical fields such as computer, information technology and integrated circuit design, digital signal processing has become increasingly important in various fields due to its advantages such as high precision, high flexibility, easy large-scale integration and multi-dimensional data processing. come out. Digital signal processing system is the carrier of digital signal processing, and its core component is digital signal processing unit. FPGA is a typical representative of reconfigurable digital processing unit. It stands out from the digital processing units and is favored by more and more users. [0003] Field Programmable Gate Arrays (Field Programmable Gate Arrays, FPGA) generally integrate dozens or even hundreds of embedded multiplier modules. T...

AI Technical Summary

Problems solved by technology

[0006] (1) It requires expensive expenses to purchase or rent ATE equipment, and needs to develop specific ATE test procedures, which increases the cost that users need to bear to a certain extent

[0007] (2) With the continuous increase of FPGA integration, chip functions become more and more complex, and the number of packaged I / O ports is limited, it is becoming more and more difficult to use ATE equipment to comprehensively test FPGA internal resources

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