77 results about "Circuit under test" patented technology

A circuit test device includes a housing. The circuit test device includes a circuit disposed in the housing and including an electromagnetic field (EMF) sensor and a signal detector coupled to the EMF sensor. The circuit test devices includes a conductor disposed on the housing and an interface extending through the housing and coupling the conductor to a circuit under test (CUT). The EMF sensor is configured to generate a signal in the presence of a time varying flow of current from the CUT in the conductor, and provide the signal to the signal detector.

This invention relates to the field of electronic measurement technology and discloses an online measurement method and system for the quality factor of resonant circuits. The method involves injecting a small-amplitude sinusoidal disturbance signal into the excitation end of the resonant circuit under test using weak electromagnetic coupling, extracting the amplitude and phase of the disturbance response using lock-in amplification technology, performing Lorentz fitting on the frequency response curve to calculate the negative 3 dB bandwidth, outputting the quality factor in real time from the ratio of the resonant frequency to the bandwidth, introducing cross-correlation narrowband filtering to compress the equivalent noise bandwidth to below 1 Hz, and having an automatic resonant frequency tracking function.

A fault injection evaluation method and system, and a computer program product and a medium. The fault injection evaluation method comprises: configuring a target number of cycles for a circuit under test (101), wherein the target number of cycles is the number of cycles during which said circuit operates after being reset; injecting a fault into said circuit (102); outputting a reset signal to said circuit, and acquiring a fault output result that is output by said circuit after the fault is injected (103); and on the basis of the fault output result and a reference output result, performing a comparison to acquire a fault evaluation result (104). By means of the method, it is not necessary to additionally provide a reference circuit, so that the structural complexity of the fault injection evaluation system can be reduced, and the consumption of resources required during evaluation can be reduced.

The embodiment of the invention discloses a current detection circuit and current detection equipment, the current detection circuit comprises a power supply input interface, a power supply output interface and a detection circuit, and the power supply output interface is connected with a circuit to be detected; the detection circuit comprises a shunt unit, a first connecting end, a second connecting end and a third connecting end, the shunt unit is connected between the first pole of the power input interface and the second connecting end, a first ampere meter is connected between the first connecting end and the second connecting end, and a second ampere meter is connected between the second connecting end and the third connecting end; when the current of the to-be-tested circuit is greater than a preset threshold value, the shunting unit is conducted, and the current drives the second ammeter to generate pointer deflection through the shunting unit; when the current of the to-be-tested circuit is smaller than a preset threshold value, the shunting unit is switched off, and the current drives the first ammeter to generate pointer deflection; wherein the first ampere meter and the second ampere meter are different in measuring range. The test efficiency and reliability can be improved.

A test pattern generation method includes: obtaining design data about a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting transition delay (TD) faults and a pre-detection fault list (PDFL) including fixed type (SA) faults respectively corresponding to detectable TD faults included in the detectable TD fault list and detectable by simulation; and generating a second test pattern for detecting the SA fault based on the design data and the PDFL.

To provide a semiconductor integrated circuit capable of continuing an operation in an analog circuit even while a scan test is executed in a digital circuit.SOLUTION: The semiconductor integrated circuit 1 includes a circuit under test 100 that generates an output signal for controlling the operation of an analog circuit in response to an input signal, a test control unit 146 that controls a scan test in the circuit under test 100, and a holding unit 170 that holds the output signal. The test control section 146 performs a scan test on the circuit under test 100 when the analog circuit is in an active state. While the scan test is executed, the holding unit 170 holds the output signal after the signal for requesting the execution of the scan test is transmitted to the semiconductor integrated circuit 1 and before the scan test is started, and outputs the held output signal so that the analog circuit can maintain the active state.SELECTED DRAWING: Figure 2

An electronic device (40) comprises: a control unit (41); output pins (45) that can be connected to an external apparatus (30); a signal generator (47) that is provided in an output circuit (46) connecting the control unit (41) and the output pins (45); input pins (49) that can be connected to the external apparatus (30); an analog to digital converter (50) that is provided in an input circuit (51) connecting the input pins (49) and the control unit (41); and a communication unit (53) that receives, from the external apparatus (30), a command for generating an output signal from the signal generator (47), and transmits the state of a circuit (20) being measured to the external apparatus (30). The circuit (20) being measured is connected between the output pins (45) and the external apparatus (30) or between the input pins (49) and the external apparatus (30).

The invention provides a chip testing circuit, a chip testing method and a chip, and is applied to the technical field of chip testing, the chip testing circuit comprises a plurality of grouping testing circuits, each grouping testing circuit comprises a plurality of tested circuit modules, and each tested circuit module comprises a plurality of IP cores; each grouping test circuit is connected with a special test channel pin; the tested circuit modules in the same grouping test circuit are connected in series with the special test channel pins, and the plurality of grouping test circuits are tested in a parallel test mode.

The invention discloses an electric control board fault prediction and self-healing method and device, and belongs to the field of electronic equipment health management, and the method comprises the steps: generating a probing excitation signal; injecting the probing excitation signal into a detected circuit of the electric control board, and synchronously capturing global field response data of the detected circuit under the combined action of the probing excitation signal and the working signal; according to the global field response data and the probing excitation signal, a real-time physical parameter map of the tested circuit is reconstructed by solving a physical inverse problem; according to the deviation between the parameter value of each node in the real-time physical parameter map and the corresponding nominal value, generating a corresponding parameter tuning instruction; and executing the parameter adjustment instruction to dynamically adjust the adjustable element parameter of the corresponding node in the tested circuit, so that the electrical performance of the node approaches to a nominal value, early-stage accurate prediction and non-inductive self-healing of the fault of the electric control board can be realized, and the stability and reliability of the control system are remarkably improved.

This application provides a method for detecting the quality of a hot plate in a plasma deposition apparatus. The hot plate is disposed within a housing, which is grounded. The hot plate contains metal wiring, which is part of the radio frequency (RF) circuitry of the plasma deposition apparatus. The method includes: constructing a first measurement circuit, which includes a measurement circuit and a first circuit under test, wherein the first circuit under test includes the metal wiring and the housing, the metal wiring and the housing forming a first parallel-plate capacitor; the measurement circuit outputs voltage signals at different frequencies and feeds back impedance spectra at the different frequencies; measuring the first impedance spectrum of the first parallel-plate capacitor using the measurement circuit; and determining whether the metal wiring of the hot plate is normal based on the first impedance spectrum.

This invention relates to the field of industrial equipment fault detection technology, and discloses a vertical spiral stirring mill live fault detection device, comprising: a housing; a detection head, detachably mounted on one end of the housing, for contacting and fixing to the circuit under test; a circuit board, disposed inside the housing, integrating a main control chip, a detection circuit module, a wireless communication module, and a data processing module; a power supply, disposed inside the housing and electrically connected to the circuit board; and an insulating rod, detachably mounted on the other end of the housing. This invention allows the detection head to be fixed to the circuit under test, enabling real-time detection of the circuit through the detection circuit module, reducing the loss of manpower, material resources, and financial resources; and it can be carried by the insulating rod, improving portability and flexibility.

The utility model relates to the field of circuit board function testing, in particular to a circuit board testing device, which comprises a power supply unit, a testing unit and a user interaction unit. And the tested circuit board is fixedly arranged on the test unit. The test unit is electrically connected to both the test unit and the user interaction unit. The power supply unit is electrically connected to the tested circuit board through a first channel and is connected to the test unit and the user interaction unit through a second channel. And the first channel and the second channel are electrically isolated. The circuit board testing device provided by the utility model is convenient and simple in testing operation, improves the working efficiency of testing the circuit board, and increases the reliability of a testing result. Meanwhile, the display interface content of the user interaction unit of the circuit board testing device is clear, the operation process is simple and convenient, and the testing function with high calibration rate and high precision can be realized. Finally, the circuit board testing device can feed back the testing state in real time, and the real-time working state of the tested circuit board can be judged conveniently.

A fault injection evaluation method and system, and a computer program product and a computer-readable storage medium. The fault injection evaluation method comprises: configuring a target number of cycles (301), wherein the target number of cycles is the number of cycles during which a circuit under test operates after being reset; at a configured fault injection moment, injecting a fault into said circuit (302); acquiring a fault output result that is output by said circuit after the fault is injected (303); and comparing the fault output result with a reference output result, so as to acquire a fault evaluation result (304).

This application discloses functional safety test circuits and methods, neural network processors, and storage media, relating to the field of functional safety technology. [Solution] The functional safety test circuit includes a configurator for generating and outputting configuration information for testing an integrated circuit under test; a plurality of test data generators for generating and outputting first test data corresponding to each of the plurality of test data generators based on the configuration information; an integrated circuit under test for processing the plurality of first test data and acquiring and outputting a plurality of second test data; and a first comparator for comparing the consistency of the plurality of second test data and acquiring a first test result of the integrated circuit under test.

The utility model discloses a low power circuit integration junction box, including casing, modular interface array, embedded control module and safety protection module, wherein, the modular interface array contains at least three kinds of specifications test terminal, and each test terminal is connected with the measured circuit board through the elastic contact, embedded control module contains microprocessor, programmable signal generator and AD conversion unit. In addition, the low power circuit integration junction box still includes power module and wireless communication module. The utility model provides junction box through using S3C2451 embedded control processor to realize the automatic measurement and judgement of low power point fast, and can save the various measurement parameters of detected through programmable signal generator and AD conversion unit, then through wireless communication module carries out data transmission, and the convenient implementation detection result inquiry and transmission have improved the detection efficiency, and the detection result also has higher measurement accuracy and good repeatability.

This disclosure provides a multi-channel testing device and method for a digital instrumentation and control system of a nuclear power plant. The multi-channel testing device includes: a load simulation module comprising a fixed resistor and an adjustable resistor; the adjustable resistor receives a first control signal from a host computer and adjusts its resistance value according to the first control signal; the fixed resistor and the adjusted adjustable resistor together constitute the target load of the device under test; an analog signal acquisition module acquires the voltage across the fixed resistor and transmits the voltage to the host computer; the host computer calculates the current signal of the circuit under test formed by the device under test and the load simulation module based on the voltage across the fixed resistor and the actual resistance value of the fixed resistor; and analyzes whether the device under test passes the test based on the sampled waveform of the current signal; both the load simulation module and the analog signal acquisition module are located inside the chassis; this solves the problem of large size of traditional testing instruments and realizes simultaneous testing of multiple devices under test, improving testing efficiency.

The invention provides a flip testing seat pressed down by a connecting rod cam mechanism, belongs to the technical field of integrated circuit board testing, and solves the technical problem that a pressing block cannot be ensured to vertically press down a tested integrated circuit. A flip testing seat pressed down by a connecting rod cam mechanism comprises a base, one side of the top of the base is fixedly connected with a connecting seat, the top of the connecting seat is connected with an upper cover through a torsional spring, the top of the upper cover is rotatably connected with a rocker, two sides of the rocker are symmetrically and slidably sleeved with cam plates, and the two cam plates are slidably connected in the upper cover. Connecting rods are rotatably connected to the interiors of the sides, close to the rocker, of the two cam plates, the other ends of the two connecting rods are rotatably connected to one side of the rocker, two Z-shaped holes are formed in one sides of the two cam plates, bearings are slidably connected to the interiors of the two Z-shaped holes, and the two bearings are rotatably connected to one side of the pressing block back plate. According to the invention, through the arrangement of the double bearings, the pressing block can be driven to vertically move up and down.

The utility model relates to the field of circuit board testing, and discloses a testing system. The test system comprises a test frame, a clamp piece and a connecting unit, the test frame comprises a platform and a vertical table, the connecting unit comprises a lamp panel module, and the lamp panel module is suitable for being electrically connected with a door lock circuit board. According to the application, the test frame is combined with the lifting bracket capable of sliding and lifting, so that flexible adjustment of the clamp piece in the vertical space position can be realized to press the door lock circuit board to be tested, the positioning requirements of the door lock circuit boards with different sizes are met, and various door lock models are supported and adapted; and the clamp piece is linked with the lifting bracket, so that the tested circuit board can be quickly fixed / released, and the test preparation time is shortened. According to the invention, the lamp panel module is used as an output device, and a light indication signal of the lamp panel module gives a test result feedback immediately, so that an operator can judge and process problems quickly and conveniently; and specifically, the control assembly uniformly manages on-off of electric connection, so that the standardization of the test process is ensured, and manual operation errors are reduced.

The utility model provides a Rogowski coil, which belongs to the field of high-frequency current measurement and comprises a Rogowski coil body and a plurality of PCBs (printed circuit boards), the PCBs are overlapped along the thickness direction of the PCBs, at least part of the PCBs which are continuously overlapped are used for winding the Rogowski coil body, and the axial direction of the Rogowski coil body is the same as the thickness direction of the PCBs. A current-carrying conductor is arranged on at least one of the PCBs where the Rogowski coil body is wound, the current-carrying conductor comprises a first interface, a second interface and a measuring line, the first interface and the second interface are connected with a tested circuit, the measuring line is connected with the first interface and the second interface, and the measuring line is arranged in the axial direction of the Rogowski coil body. Along the axial direction of the Rogowski coil body, the projection of the measuring line is located in the projection of the coil of the Rogowski coil body. Alternating current in a measured circuit flows through the current-carrying conductor to generate a magnetic field, induced electromotive force is generated in the Rogowski coil body, the current in the measured circuit is measured, and the current measurement precision is high.

The invention relates to a signal generation device, a to-be-tested circuit and a signal generation method. The device comprises a configuration module; the initial value of the counter is configured by the configuration module; the finite-state machine sends a counter enabling signal to the counter when the finite-state machine is in a test state, the counter is enabled in response to the counter enabling signal, and the finite-state machine sends the counter enabling signal to the finite-state machine when the finite-state machine is in a test state. The finite-state machine is used for receiving an initial numerical value and generating a state skipping signal for skipping the test state of the finite-state machine when the counting value of the counter reaches the initial numerical value, and the finite-state machine skips the test state according to the state skipping signal and generates a test function signal corresponding to the skipped test state. Therefore, the test function signal can be automatically generated in the circuit to be tested, and the test function signal does not need to be provided through an ATE.

The invention relates to the technical field of electrical safety, and provides an electric leakage detection device and method based on a Helmholtz coil and a Hall chip, and the device comprises a Helmholtz coil assembly, a Hall sensing module, a signal processing module, and an execution mechanism. The Helmholtz coil assembly sleeves the outer sides of a phase line and a zero line of a detected circuit and is used for sensing a magnetic field generated by leakage current in the circuit; the Hall sensing module is arranged in the central area of the Helmholtz coil assembly and is used for detecting the magnetic field intensity and converting the magnetic field intensity into an electric signal; and the signal processing module processes and analyzes the electric signal, and drives the actuating mechanism to cut off the circuit when electric leakage is judged. Compared with a traditional zero-sequence mutual inductor and leakage protection chip scheme, the Helmholtz coil and Hall chip combined scheme has the advantages of being high in detection sensitivity, high in response speed, good in linearity, excellent in temperature stability and the like, and can be widely applied to various electrical safety protection fields.

A fault injection assessment method and system, a computer program product, and a medium, the fault injection assessment method comprising: configuring a target cycle number for a circuit to be tested, the target cycle number being a cycle number of operation after the circuit to be tested is reset; injecting a fault into the circuit to be detected; outputting a reset signal to the to-be-tested circuit, and obtaining a fault output result output by the to-be-tested circuit after the fault is injected; and comparing the fault output result with a reference output result to obtain a fault evaluation result. By adopting the scheme, a reference circuit does not need to be additionally arranged, the structural complexity of the fault injection evaluation system can be reduced, and resources required to be consumed during evaluation can be reduced.

The invention discloses a fault injection evaluation method and system, a computer program product and a medium, and the method comprises the steps: configuring a target period number which is the operation period number of a to-be-tested circuit after the to-be-tested circuit is reset; injecting a fault into the to-be-tested circuit at the configured fault injection moment; obtaining a fault output result output by the to-be-tested circuit after the fault is injected; and comparing the fault output result with a reference output result to obtain a fault evaluation result. According to the scheme, fault injection and fault evaluation at any moment can be realized.

The invention relates to an arc detection circuit and arc detection equipment. The arc detection circuit comprises a differential amplification module used for receiving a first voltage signal representing a target current in a detected circuit and outputting a second voltage signal; the amplitude of the second voltage signal is in direct proportion to the time change rate of the target current; the edge detection module is used for detecting an edge in the second voltage signal and outputting a target pulse signal when an edge jump condition of the second voltage signal meets a preset jump condition during arc generation; the threshold comparison module is used for receiving the first voltage signal and outputting a target comparison signal when the first voltage signal is greater than a preset threshold voltage; and the logical operation module is used for outputting an arc existence signal when receiving the target comparison signal and the target pulse signal. The arc detection circuit can improve the arc detection speed.

This utility model relates to the field of PCB board testing technology and discloses a PCB board that can replace the bed-of-pipe wiring of test fixtures. It includes: a PCB support base plate, a PCB encapsulation cover plate, and a PCB board body. The PCB encapsulation cover plate is fixedly connected to the top surface of the PCB support base plate, and the PCB board body is slidably connected to the inner side of the PCB encapsulation cover plate. A buffer guide assembly is disposed between the PCB support base plate and the PCB board body. A pin connection adjustment assembly is disposed on the side of the PCB board body. This utility model improves stability and reliability through buffer guidance, enhances flexibility and shortens test preparation time through pin adjustment, reduces maintenance and customization costs and test errors by replacing traditional probes with a PCB board, and also reduces contact pressure to protect the circuit board under test. It solves the problems of complex process, high cost, poor flexibility and adaptability, and easy damage to test points associated with traditional bed-of-pipe wiring.

The invention discloses an in-situ test system and method for a high-temperature integrated circuit, relates to the technical field of integrated circuit test, and aims to solve the problem that an existing high-temperature test method for the integrated circuit cannot accurately test electrical parameter performance at a target temperature. The system at least comprises a test socket, a constant temperature source, a heat insulation device, a test daughter board, a test mother board and automatic test equipment, an integrated circuit to be tested is mounted on the test daughter board through the test socket, and the heat insulation device is in contact connection with one surface, where the test socket is mounted, of the test daughter board and at least covers the test daughter board except the test socket; the constant-temperature source comprises a heat flow cover, the heat flow cover is buckled on the outer side of the test socket, and a closed space is formed by the heat flow cover and the heat insulation device; the test daughter board is plugged on the test mother board, and the test mother board is assembled on the automatic test equipment. The high-temperature integrated circuit in-situ test system provided by the invention is used for improving the accuracy of testing the electrical parameter performance of the integrated circuit in a high-temperature environment.

This invention relates to the field of electronic measurement technology and discloses an online measurement method and system for the quality factor of resonant circuits. The method involves injecting a small-amplitude sinusoidal disturbance signal into the excitation end of the resonant circuit under test using weak electromagnetic coupling, extracting the amplitude and phase of the disturbance response using lock-in amplification technology, performing Lorentz fitting on the frequency response curve to calculate the negative 3 dB bandwidth, outputting the quality factor in real time from the ratio of the resonant frequency to the bandwidth, introducing cross-correlation narrowband filtering to compress the equivalent noise bandwidth to below 1 Hz, and having an automatic resonant frequency tracking function.

The invention relates to the field of current detection, in particular to AKYSC100uA digital ultramicro high-precision direct current detection equipment and method. The detection device comprises: a shielding housing unit comprising a housing made of a conductive material to provide stable electromagnetic shielding and mechanical support; the circuit board is installed in the shell, and an analog signal area, a digital processing area and a power management area are arranged on the circuit board; and the signal acquisition and protection unit comprises an input interface arranged on the shell, and an overload protection module, a micro-current sampling module and a signal conditioning module which are arranged on the circuit board. The device ingeniously balances the measurement sensitivity and the influence on a measured circuit, ensures that a detection signal which is strong enough is prevented from being submerged by noise, and also reduces the interference of an instrument on the working state of the measured circuit during measurement, so that high accuracy and high authenticity are realized in micro current measurement.

The utility model belongs to the field of test circuit provides a kind of switch circuit test edition, including connector and multiple test circuits, connector is used to with the plug-in connection of measured circuit, it has the output pin of multiple output switch signals, the pin of multiple output switch signals is different respectively in test circuit, multiple test circuits all include first test unit and second test unit, first test unit includes first triode and buzzer, the B pole of first triode is connected with output pin, its E pole is grounded, its C pole is connected with buzzer negative pole, second test unit includes second triode and LED, the B pole of second triode is connected to the same output pin with first triode, the E pole of second triode is grounded, its C pole is connected with the negative pole of LED, the buzzer of multiple test circuits is all powered by DC power supply, the anode of the LED of multiple test circuits is all connected to the same power chip;The utility model can solve the problem that the electric signal detection result of precision integrated circuit in the prior art is not intuitive enough.

A test pattern generating method includes obtaining design data with respect to a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation; and generating a second test pattern for detecting SA faults based on the design data and the PDFL.