11 results about "Interrupt flag" patented technology

The application discloses a cold backup control method and controller of a processing core and an integrated circuit, relates to the technical field of processors, and comprises the following steps: in a current evaluation period, the cold backup controller can collect running state information of a target processing core corresponding to the cold backup controller, and adopts a preset scoring rule to evaluate the running state information, so that a target score of the target processing core in the current evaluation period is obtained. In a continuous preset number of periods, when the scores of the target processing core are all within a preset score threshold range, an interruption flag of the target processing core is read from an interruption controller, a task allocation flag of the target processing core is read from a task scheduler, and then whether the target processing core meets a cold backup condition is determined according to the interruption flag and the task allocation flag; if yes, a cold backup switching operation is performed on the target processing core. In this way, the response is timely, and the cold backup controller is only responsible for the processing core corresponding to the cold backup controller, so that the control granularity is relatively fine.

Computer systems, service processing methods, and chips are provided in this disclosure. In one implementation, a computer system comprises an interrupt status register, a permission management register, a processor, a target storage space, and a memory storing programming instructions for execution by the processor to: set a flag corresponding to the first interrupt in the interrupt status register to a first interrupt flag and a flag corresponding to the first interrupt in the permission management register to a first call flag, wherein the first interrupt flag and the first call flag indicate whether access to the target storage space is allowed, determine whether to allow the processor to access the target storage space, and obtain first information in the target storage space in a TEE mode if determining that the processor is allowed to access the target storage space; and execute the target service based on the first information.

This invention relates to the field of virtualization orchestration technology, specifically to a virtualization orchestration system and method for industrial control. The system includes a task extraction module, a node behavior monitoring module, a stability assessment module, an orchestration load adjustment module, and a control task migration module. This invention, by collecting control task scheduling mapping tables and execution instruction queues, and combining loop control flags and interrupt flags to identify closed-loop characteristics of scheduling cycles, can effectively identify sets of orchestratable tasks. It calculates behavior success rates based on parameters such as node response latency and task completion rates, and performs node stability screening to classify control nodes by stability level. By setting release thresholds to form a scheduling priority list, it determines task migration timing based on task dwell time and I / O completion status, and uses behavior pattern matching to accurately select migration targets, significantly improving the stability of task scheduling, the accuracy of resource allocation, and the adaptability of control logic.

This disclosure provides an optical module and a method for improving optical module communication. The MCU monitors the level of the module selection pin. Upon detecting a level change in the module selection pin, it sets an interrupt flag to a first value. If the interrupt flag is read as the first value, an interrupt function is initiated. The interrupt function sets the interrupt flag to a second value. The interrupt function then determines whether the monitored level is low. If it is high, the interrupt function closes the first I2C interface; if it is low, the interrupt function opens the first I2C interface, allowing the host computer and the optical module to communicate normally via I2C. By setting the interrupt flag to the second value before determining whether the monitored level is low, the interrupt function avoids clearing the interrupt flag set when the module selection pin changes from high to low, allowing the interrupt function to open the first I2C interface and thus enabling normal I2C communication between the host computer and the optical module.

The invention relates to the technical field of IEC tasks, in particular to an IEC task scheduling method and device based on hardware interruption, equipment and a medium, and the method comprises the following steps: determining an interruption number corresponding to an interruption flag bit and an interruption execution program corresponding to the interruption number by responding to the interruption flag bit set in a hardware peripheral; writing the interrupt number into a preset event bitmap according to the interrupt execution program to obtain an updated event bitmap and trigger an interrupt scheduler of the interrupt execution program; analyzing the updated event bitmap according to the interrupt scheduler to obtain an IEC task ID corresponding to at least one analysis interrupt number in the updated event bitmap; and according to the priority of each IEC task ID, inserting each IEC task ID into a priority ready queue and executing task scheduling, thereby realizing real-time response and execution of the IEC tasks based on hardware interruption. And the response delay of the system to high-priority external events is optimized.

This disclosure provides systems, methods, and devices for memory systems that support detecting and tracking a quantity of errors in memory using a counter and indicating the detection and quantity of errors using an interrupt flag. In a first aspect, a method includes, at a hardware of a memory system detecting one or more errors at a memory. The method includes counting a quantity of the one or more errors until the quantity is equal to or greater than a threshold quantity of errors. The method includes recording the quantity of errors and an error type in an error log. The method includes transmitting an indication that the quantity of errors of the memory is equal to or greater than the threshold. Other aspects and features are also claimed and described.

The invention relates to a method for controlling a low power consumption mode of embedded firmware and storage equipment, and belongs to the field of power consumption management. The method comprises the following steps: in response to a received instruction of entering a low-power-consumption mode, traversing a task circular queue of SSD kernel firmware, and judging whether a to-be-run task exists or not and whether interruption occurs or not; if it is determined that there is no to-be-run task in the preset time period and no interruption occurs, setting an interruption flag, and enabling the instruction entering the low-power-consumption mode to be invalid; after the task circular queue is traversed again, the interrupt mark is cleared away, and the SSD kernel firmware is controlled to enter the low-power-consumption mode by executing the instruction for entering the low-power-consumption mode. According to the embodiment of the invention, the response time delay of the low power consumption mode to the embedded firmware is reduced.

Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

The invention discloses a dynamic load balancing mapping method and system based on interrupt transaction combination. The method comprises the following steps: an interrupt synchronization processing step; an interruption mark setting step; a load state acquisition step; a dynamic combination control step; a channel mapping step; a target source processing step; and a closed loop feedback step. The invention also comprises a system for implementing the method. According to the method, the transformation of an interrupt scheduling normal form is realized through'dynamic load perception + hardware closed-loop architecture + elastic scheduling strategy ', firstly, post statistics is replaced by real-time quantitative load perception, and the problem that a scheduling decision and a real-time demand are disjointed is solved; secondly, due to full-hardware implementation, software intervention overhead is eliminated, and scheduling delay is reduced to a single-cycle level; and finally, an elastic combination mechanism and a priority collaboration strategy ensure the deterministic response of the key interruption.

This application relates to a CXL system, a device handshake method, a computer device, a readable storage medium, and a program product. The method involves: reading the value of a first attribute field in an address window; if the value of the first attribute field is a second preset value; setting the value of the second attribute field in the address window to the second preset value, updating the address window information, and then setting the value of the second attribute field in the address window to the first preset value; if the CXL host bridge detects that the value of the second attribute field in the address window has been set to the first preset value, generating an interrupt flag; and a coprocessor, upon detecting the interrupt flag, copying the address window information to the interconnect bus via an interrupt service routine and setting the value of the first attribute field in the first shadow register to the first preset value; and the CXL host bridge synchronizing the value of the first attribute field in the first shadow register to the first capability register. This avoids bus hangs.

The invention discloses a cold standby control method of a processing core, a cold standby controller and an integrated circuit, and relates to the technical field of processors, and the method comprises the steps: in a current evaluation period, the cold standby controller can collect the operation state information of a target processing core corresponding to the cold standby controller, employs a preset scoring rule, carries out the evaluation of the operation state information, and carries out the evaluation of the operation state information; and obtaining a target score of the target processing core in the current evaluation period. Reading an interrupt mark of the target processing core from an interrupt controller and a task allocation mark of the target processing core from a task scheduler when the scores of the target processing core are determined to fall into a preset score threshold range in a continuous preset number of cycles, and then allocating the target processing core to the task scheduler according to the interrupt mark and the task allocation mark. And determining whether the target processing core meets a cold standby condition, and if so, executing a cold standby switching operation on the target processing core. Therefore, the response is timely, and the cold standby controller is only responsible for the corresponding processing core, so that the control granularity is relatively fine.