5 results about "Interrupt flag" patented technology

The application discloses a cold backup control method and controller of a processing core and an integrated circuit, relates to the technical field of processors, and comprises the following steps: in a current evaluation period, the cold backup controller can collect running state information of a target processing core corresponding to the cold backup controller, and adopts a preset scoring rule to evaluate the running state information, so that a target score of the target processing core in the current evaluation period is obtained. In a continuous preset number of periods, when the scores of the target processing core are all within a preset score threshold range, an interruption flag of the target processing core is read from an interruption controller, a task allocation flag of the target processing core is read from a task scheduler, and then whether the target processing core meets a cold backup condition is determined according to the interruption flag and the task allocation flag; if yes, a cold backup switching operation is performed on the target processing core. In this way, the response is timely, and the cold backup controller is only responsible for the processing core corresponding to the cold backup controller, so that the control granularity is relatively fine.

Computer systems, service processing methods, and chips are provided in this disclosure. In one implementation, a computer system comprises an interrupt status register, a permission management register, a processor, a target storage space, and a memory storing programming instructions for execution by the processor to: set a flag corresponding to the first interrupt in the interrupt status register to a first interrupt flag and a flag corresponding to the first interrupt in the permission management register to a first call flag, wherein the first interrupt flag and the first call flag indicate whether access to the target storage space is allowed, determine whether to allow the processor to access the target storage space, and obtain first information in the target storage space in a TEE mode if determining that the processor is allowed to access the target storage space; and execute the target service based on the first information.

This disclosure provides an optical module and a method for improving optical module communication. The MCU monitors the level of the module selection pin. Upon detecting a level change in the module selection pin, it sets an interrupt flag to a first value. If the interrupt flag is read as the first value, an interrupt function is initiated. The interrupt function sets the interrupt flag to a second value. The interrupt function then determines whether the monitored level is low. If it is high, the interrupt function closes the first I2C interface; if it is low, the interrupt function opens the first I2C interface, allowing the host computer and the optical module to communicate normally via I2C. By setting the interrupt flag to the second value before determining whether the monitored level is low, the interrupt function avoids clearing the interrupt flag set when the module selection pin changes from high to low, allowing the interrupt function to open the first I2C interface and thus enabling normal I2C communication between the host computer and the optical module.

This disclosure provides systems, methods, and devices for memory systems that support detecting and tracking a quantity of errors in memory using a counter and indicating the detection and quantity of errors using an interrupt flag. In a first aspect, a method includes, at a hardware of a memory system detecting one or more errors at a memory. The method includes counting a quantity of the one or more errors until the quantity is equal to or greater than a threshold quantity of errors. The method includes recording the quantity of errors and an error type in an error log. The method includes transmitting an indication that the quantity of errors of the memory is equal to or greater than the threshold. Other aspects and features are also claimed and described.

This application relates to a CXL system, a device handshake method, a computer device, a readable storage medium, and a program product. The method involves: reading the value of a first attribute field in an address window; if the value of the first attribute field is a second preset value; setting the value of the second attribute field in the address window to the second preset value, updating the address window information, and then setting the value of the second attribute field in the address window to the first preset value; if the CXL host bridge detects that the value of the second attribute field in the address window has been set to the first preset value, generating an interrupt flag; and a coprocessor, upon detecting the interrupt flag, copying the address window information to the interconnect bus via an interrupt service routine and setting the value of the first attribute field in the first shadow register to the first preset value; and the CXL host bridge synchronizing the value of the first attribute field in the first shadow register to the first capability register. This avoids bus hangs.