62 results about "System time" patented technology

Embodiments of the invention disclose a method, a device and a system for processing a wake-up lock, and belong to the field of computer technology. The method comprises the following steps: detecting whether a wake-up lock is in a working state, and if so, obtaining a wake-up parameter corresponding to the wake-up lock, wherein the wake-up parameter comprises an arithmetic operation corresponding to the wake-up lock and an application program corresponding to the wake-up lock; judging whether the arithmetic operation corresponding to the wake-up lock requires a sensor of a terminal; if not, generating a wake-up transfer request according to the wake-up parameter, sending the wake-up transfer request to a server, and releasing the wake-up lock, wherein the server is used for executing the arithmetic operation corresponding to the wake-up lock; and receiving a wake-up message sent by the server, and waking up the terminal according to the wake-up message. By adopting the method disclosed by the invention, after a display screen of the terminal is closed, the system time occupancy of the application program can be reduced, the power consumption of the terminal is reduced in the case that the display screen of the terminal is closed, and the standby time of the terminal is prolonged.

Disclosed are a system on chip, method and device supporting time synchronization, and a storage medium, which relate to the technical field of time synchronization, the system on chip synchronizes the time of an STBM in the system on chip with the time of an off-chip master clock through a first processor core according to a first preset period; based on the first time of the STBM after time synchronization, calibrating a hardware clock of the first network card to obtain a first time reference; calibrating the time of the STBM based on the first time to obtain a second time reference; synchronizing, by the second processor core, the time of the second network card with the time of the first time reference based on a first time difference between the first network card and the second network card; and synchronizing the system time with the time of the second time reference based on a second time difference between the second time reference and the system time of the operating system. According to the system, double time references can be obtained, sub-microsecond-level synchronization precision is realized, and the strict requirement of a high-precision time synchronization scene on time synchronization precision is met.

The invention provides a method and a device for realizing time migration, a storage medium and a computer program product. The method comprises the following steps: under the condition that a target process calls a time correlation function in a kernel, acquiring context information when the target process runs through a time migration simulation program pre-mounted in the time correlation function; based on the context information, determining a time migration strategy matched with the target process as a target time migration strategy; and according to the target time migration strategy, determining the system time after migration, and returning the system time to the target process. According to the invention, the flexibility of time migration can be improved.

The application discloses a time synchronization method, device, equipment and medium, relates to the technical field of time synchronization, and is applied to an embedded device and comprises the following steps: receiving an analog second pulse signal sent by an external device by using a general input and output pin, and recording a raw system timestamp corresponding to an arrival time of the signal; compensating the raw system timestamp according to a preset delay compensation parameter, and performing jitter filtering processing on the compensated timestamp to obtain a processed timestamp; and reporting the processed timestamp to a PPS subsystem, so that a preset time synchronization service calibrates a system time of the embedded device based on the processed timestamp read from the PPS subsystem. The application can realize high-precision time synchronization of the embedded device by using the external device to simulate a PPS signal.

The invention provides a main and standby switching method and system for a water dispatching automation system, and relates to the field of water dispatching automation and data processing. The method aims at solving the problems that in an existing method, business event flow sequential logic is ignored, and instructions are prone to being disordered and lost due to switching. The method is applied to a framework comprising a main system, a standby system and a time source, and the main system and the standby system are synchronous in time. When executing the water dispatching control instruction, the main system generates a water dispatching event containing instruction content and a timestamp, and stores the water dispatching event in a shared event sequence cache region; the standby system periodically pulls an event, simulates execution after verification by a business rule engine in combination with an associated context, constructs an event node tree diagram with a weight, and prunes based on an actual result; and when the switching is triggered, comparing the actual result of the main system with the execution sequence of the standby system, matching an adaptive path, and avoiding error instruction marks. The method guarantees the time sequence consistency and logic correctness of the event flow, achieves the intelligent seamless switching of a main system and a standby system, and guarantees the continuous and stable operation of a water dispatching service.

The present disclosure provides a method for processing application information, an electronic device, and a storage medium, and relates to the technical field of communications. The method includes: determining a target time period based on a current system time and historical usage information of at least one application; and screening usage record information of the at least one application according to the determined target time period to obtain target information, wherein the target information is information generated in a historical time period matched with the target time period, and the usage record information is usage information of the at least one application in a plurality of time periods.

The invention provides a time synchronization method, device and system of a master device and a slave device, computer equipment and a storage medium, and relates to the technical field of wireless transmission, the master device sends a first broadcast packet to the slave device, the first broadcast packet is sent only once, and therefore it is ensured that when the time difference between the master device and the slave device is calculated, the time difference between the master device and the slave device is calculated. The time difference is corresponding to receiving and transmitting of the same broadcast packet, and when the propagation time of electromagnetic waves between two devices is ignored, the time related to the time difference corresponds to the same world time, so that the system time of the slave device can be accurately calculated; the clock synchronization updating between the master device and the slave device can be completed under the condition of considering broadcast delay.

The application discloses a method for protecting time stamp of embedded system, which is executed based on a time stamp protection time correction module in the embedded system, and comprises the following steps: step S1, optimizing the floating point operation function of the compiling tool used by the time stamp protection time correction module, and eliminating the problem of abnormal zero of the floating point operation result; and step S2, the time stamp protection time correction module creates a time system data receiving communication link based on a preset configuration, and configures the time system data receiving timeout parameter of the communication link; the application solves the technical problems of time stamp abnormality, false time correction and poor stability caused by step-by-step time correction, operation defects of the compiler, and coupling of the time correction module and the service data processing module.

This invention belongs to the field of BMC system time synchronization technology, specifically providing a method, apparatus, device, and medium for the first time synchronization during the BMC startup phase. The method includes the following steps: During the BMC startup phase, determining whether the time of the BMC management controller and the server has been successfully synchronized; determining whether a configuration file exists; if synchronization is successful and the configuration file exists, obtaining the last recorded time stored in the configuration file; comparing the obtained time with the time of the synchronized server; if the obtained time is faster than the synchronized server time, setting the obtained time as the current time of the BMC management controller; otherwise, using the synchronized server time as the current time of the BMC management controller; and periodically recording the current BMC management controller time into the configuration file during the startup process. This reduces the difference from the standard time caused by abnormal synchronization time during the first synchronization phase of the BMC startup phase.

The invention relates to an interrupt response time detection method and device, equipment, a medium and a program product. The interrupt response time detection method comprises the steps that in response to monitoring that a timer used for interrupt response time detection in an operating system is overtime, a detection program reads a first timestamp from character equipment in a kernel mode of the operating system and triggers the character equipment to send an event notification signal to the detection program, the detection program is a program used for detecting the interrupt response time in a user mode of the operating system, and the first timestamp is a timestamp when the operating system generates the current interrupt; in response to the received event notification signal, the detection program calls a callback interface corresponding to the event notification signal in a user mode in the operating system, and obtains a second timestamp from the callback interface, the second timestamp being a timestamp that the operating system starts to process the current interruption by using the callback interface; based on the first timestamp and the second timestamp, the detection program determines an interrupt response time for the current interrupt.

The embodiment of the invention provides a handshake method and device for time synchronization of a multi-modular redundancy computer system, and the method comprises the steps: transmitting a synchronization request instruction to a handshake synchronization unit of a local machine of each module by a CPU (Central Processing Unit) of each module according to a preset time window; a handshake pulse signal is generated through the pulse generation logic subunit of each module, and the handshake pulse signal is sent to other modules; when a handshake pulse signal of the corresponding module is detected by a pulse edge detection subunit, corresponding to other modules, in the local machine of each module, recording a handshake pulse receiving moment; aiming at each module, the module has the handshake pulse receiving moment and the own handshake pulse generating moment in the preset synchronization time period at the same time, which indicates that the current handshake synchronization of the module and the module emitting the handshake pulse corresponding to the handshake pulse receiving moment is successful. Hardware logic is adopted to realize handshake synchronization logic among multiple modes, the cost is low, and handshake is fast.

The invention provides a time synchronization method and system based on satellite common view and time transfer, and belongs to the technical field of time synchronization, and the method comprises the following steps: confirming a GNSS system time source and at least two external wired time sources, and carrying out the credibility detection of the GNSS system time source; performing anti-cheating detection on the external wired time sources, confirming the priority, and sorting the external wired time sources based on the priority; when the time source of the GNSS system passes the credibility detection, the time source of the GNSS system is used as a main time source; when the time source of the GNSS system does not pass the credibility detection, selecting an external wired time source with the highest priority to replace the main time source; and calibrating a local endogenous time source of the master station based on the time signal of the master time source, generating master station synchronization time, and performing slave station time synchronization. According to the method, the GNSS system time source and the external wired time source are detected at the same time, the time source with the highest credibility is selected for synchronization, and the accuracy and safety of time synchronization are improved.

This application discloses a device time correction method, apparatus, device, storage medium, and program product, relating to the field of embedded technology. The method, applied to embedded devices, includes: starting a time correction service via a local configuration file when the device boots up, and setting it as a prerequisite service for business services to ensure that business services start subsequently; calling the time correction service to perform corresponding time correction operations: if the hardware detection information of the real-time clock module indicates a hardware fault or absence, then performing anomaly detection on the current system time; if the current system time is abnormal, correcting the system time using a target time generated and pre-configured based on device batch information. This time correction scheme does not rely on an external network, is automated and timing-controllable, and based on a local time source, enables embedded devices to achieve time self-correction in offline deployment environments, ensuring time consistency and the reliability of business functions even without a network.

This application provides a multi-source hierarchical clock synchronization method and system for a cockpit-rider fusion domain controller, which can solve the problem of clock inconsistency among multiple operating system domains using a purely software-based approach. It integrates three time sources—MCU RTC, NTP, and GNSS—through a cross-domain distributed message bus. Upon startup, the system clock is coarsely adjusted to a roughly correct initial time using the MCU's RTC. Then, fine-tuning is performed using network time. During fine-tuning, the system time value is not directly modified; instead, a PI controller calculates frequency adjustment, slightly speeding up or slowing down the system clock frequency, ultimately causing the time deviation between the three system domains to gradually converge to zero.

The invention discloses an enhanced clock synchronization system and method based on PID (Proportion Integration Differentiation) feedback control, according to the scheme, for two clock nodes which are synchronous with each other and have a master-slave relationship, PID feedback control on time offset is carried out on a slave clock node, and the PID feedback control on the time offset is carried out on the slave clock node; performing linear combination on the time offset according to proportion, integration and differentiation (PID) to form adjusted time offset, and calculating the system time based on the adjusted time offset to obtain corrected system time; time offset calculation is further carried out based on the corrected system time, and new time offset is obtained through calculation; next, the new time offset is subjected to the next round of PID feedback control calculation and system time correction calculation, so that PID feedback control is carried out to adjust the time offset, the corrected system time is adjusted in real time, the convergence time is shortened, and the synchronization error is reduced.

The invention relates to the technical field of clock generation, in particular to a high-performance clock generation method and device based on a flexible H tree. The method comprises the following steps: generating a reference clock signal by adopting a multi-channel phase-locked loop array, and carrying out dynamic phase calibration through a digital time converter to obtain a final reference clock signal; constructing a flexible configurable H-tree clock network structure, and forming a trunk and branch topological structure by adopting a high-drive buffer; the useful deviation of a clock path is adjusted in combination with a clock concurrency optimization strategy; environment parameters are collected, clock adjustment is carried out through the environment parameters, and clock signals meeting performance requirements are generated. Therefore, the problems of insufficient adaptive capacity to the environment, delay imbalance of part of paths, incapability of realizing sensing and real-time compensation, reduction of time sequence precision and the like due to the fact that the H-tree structure design is solidified and a dynamic adjustment mechanism is lacked in the prior art are solved, and the phase consistency of clock signals, the system time sequence margin and the energy efficiency ratio are remarkably improved.

The invention belongs to the technical field of intelligent driving, and provides an intelligent driving system multi-source redundant time synchronization method and system and application, and the method comprises the steps: constructing three levels of redundant time sources which are arranged in a descending order according to priorities; after the intelligent driving system is powered on, the effectiveness of time sources is detected according to the priority sequence, double-source matching operation is executed, the effective time source with the highest priority is selected as a time service main source, and the time service main source is locked and not switched in the power-on period; an area controller is bypassed through an end-to-end direct connection synchronization mechanism, and a high-precision time synchronization full link is directly established with an intelligent driving area controller; and after power-off, the synchronization time of the intelligent driving domain controller is written into the nonvolatile memory, so that the continuity of the system time is maintained based on the third-level source when both the first-level source and the second-level source fail. According to the invention, the time synchronization effect of full-scene time continuity, high precision and no jump / conflict at the source end can be realized.

The invention relates to a log hierarchical synchronization system based on an ARM-MCU (Advanced RISC Machine-Microprogrammed Control Unit) heterogeneous system, which belongs to the technical field of embedded systems and is characterized in that an MCU slave is connected with an FPGA (Field Programmable Gate Array) module through an LVDS (Low Voltage Differential Signaling) bus, and the FPGA module is connected with an ARM host through the Ethernet; the MCU slave is used for sending the generated log to the FPGA module and storing the log containing the key event through the annular buffer area; the FPGA module is used for packaging the log to obtain a UDP (User Datagram Protocol) message and sending the UDP message to the ARM host; and the ARM host is used for analyzing the UDP message to obtain the log, obtaining the system time, writing the log and the system time into a log file, and performing hierarchical storage on the log based on the priority of the log. According to the system provided by the invention, timestamps are uniformly recorded by the ARM, so that the problem of time asynchronization is avoided, logs are uniformly recorded and managed by the ARM end, million-level log recording is supported, and complete system operation logs can be stored.

The invention discloses a master station-terminal module distributed clock synchronization method based on PID closed-loop control, and belongs to the technical field of industrial automatic control clock synchronization. Comprising the following steps: S1, synchronizing clocks of a master station and a slave station by measuring and compensating network transmission delay and node crystal oscillator deviation, and establishing a system time reference; s2, the slave station periodically sends a data frame with a timestamp T1 to the terminal module through a bus by taking the Sync0 signal as a reference; s3, the terminal module records local time T2 while receiving the data frame, compares the local time T2 with the timestamp T1 in the frame, and calculates clock skew; s4, the terminal module selects PID parameters according to the deviation, and a local clock is adjusted in a closed-loop mode to enable the clock deviation to approach zero; and S5, repeating the process in each communication period, and keeping all the terminal modules consistent with the master station for a long time through continuous iteration. And a Sync0 signal is used as a time reference and extends to an RS485 bus, and microsecond-level clock synchronization of a terminal module and a master station is realized through a three-level synchronization architecture, so that the requirements of scenes such as multi-axis servo control and high-speed data acquisition on high-precision time consistency are met.

The invention discloses a dual-system time synchronization method and device, a storage medium and a program product, and relates to the technical field of data transmission, and the method comprises the steps that a first system obtains timestamp information of data transmission between the first system and a second system, the timestamp information at least comprises a first timestamp and a second timestamp for data transmission from the first system to the second system, and a third timestamp and a fourth timestamp for data transmission response from the second system to the first system, and determining the time delay length between the first system and the second system according to the timestamp information, and sending the first time point and the delay duration of the first system to the second system. The first time point is a time point when the first system transmits the delay duration to the second system in a one-way mode, and the second system carries out time synchronization processing based on the received first time point and the delay duration. According to the invention, the precision of dual-system time synchronization is improved.

The embodiment of the application provides a kind of identity generation method, device and electronic equipment, since current system time is not later than previous system time, it indicates that system time is back dialled after the last time generating identity, therefore, the application can be registered in the case where system time is back dialled, new copy identification for target instance, and since the first copy identification newly registered is not registered copy identification before, and the identity is generated based on the copy identification registered in the application, it can be seen that the identity is not generated based on the copy identification newly registered before, so the identity generated based on the copy identification newly registered is not repeated with the identity generated before, therefore, the application can be registered in the case where system time is back dialled, avoid generating repeated identity.

The invention belongs to the technical field of network communication, and particularly relates to an SNTP message sending method and device, a storage medium and a program product. According to the method, the field of the sending time in the SNTP message is filled with 0 in the application packaging link of SNTP message sending, the FPGA system sending time is obtained by adding the current FPGA system time to a set time interval threshold value in the driving processing link, and the set time interval threshold value is larger than or equal to the time needed by a driver to send the SNTP message to an FPGA module; the method comprises the following steps of: calculating UTC time corresponding to FPGA system sending time according to a corresponding relation between the UTC time and FPGA system time, further updating the sending time in a received SNTP message to the corresponding UTC time, and then sending the SNTP message by an FPGA module according to the calculated FPGA system sending time. According to the SNTP message sending method, the time synchronization precision of the SNTP message is ensured, the implementation cost and difficulty are reduced, and the problems that an existing network time synchronization method is complex in operation and high in implementation cost are solved.

The application provides a multi-source time tracking tamper-proofing method and system in an offline environment. The method comprises: comparing system time and event log time to identify mutation anomalies; in the case where no mutation occurs, calculating the time rollback amount when the current system time is less than the last recorded time, determining whether the time rollback amount reaches the preset time threshold, increasing the anomaly count if yes, and ignoring if no; calculating the time difference when the current system time is greater than the last recorded time, accumulating the time difference to the partial seconds, and converting to accumulated whole days when the preset total seconds per day are reached; binding and encrypting the accumulated whole days, the partial seconds and the hardware hash value for storage, and synchronizing to the registry for backup. The system comprises a multi-source time acquisition module, an anomaly grading detection module, a split accumulation module and a binding storage module. The application realizes the determination, interception and fault handling of offline time tampering.

The invention relates to the technical field of computers, and discloses an acceleration method and device, equipment, a medium and a program product. In the method, a first interface is displayed, the first interface comprises first information, and the first information is used for indicating the starting moment of a first panic buying event and / or the difference value between the starting moment of the first panic buying event and the system time of the electronic equipment; obtaining first information, and determining a demand level of the first panic buying event, the demand level being used for indicating an emergency degree of the first panic buying event; based on the demand level of the first panic buying event, determining a first acceleration strategy corresponding to the demand level of the first panic buying event; and after the first information meets a set first condition, adjusting the running state of the electronic equipment based on a first acceleration strategy. Therefore, the demand level of the panic buying event can be determined based on the content of the first interface, and the corresponding acceleration strategy is determined based on the demand level, so that the system performance is improved, and the probability of successful panic buying of the user is improved.

The application provides a time synchronization method and device to improve the reliability, effectiveness and convenience of the time synchronization function of a BMC system. The method is applied to a BMC system, and the steps include: sending a time synchronization request to a NOS according to a first trigger condition, wherein the time synchronization request is used to request the NOS to send time information serving as a basis for time synchronization of the BMC system; receiving a time synchronization instruction from the NOS, wherein the time synchronization instruction carries the time information; and in response to the time synchronization instruction, obtaining the time information from the time synchronization instruction and synchronizing the time in the BMC system according to the time information.

The invention discloses a clock synchronization method and device for an underground pipe gallery. The method comprises the following steps: receiving a first message sent by master clock equipment, and recording receiving time as a first timestamp; a second message and a second timestamp sent by the master clock device are received, and the second timestamp is the current system time of the master clock device; sending the third message to the master clock device, and recording the sending time as a third timestamp; a fourth message and a fourth timestamp sent by the master clock device are received, and the fourth timestamp is the time when the master clock device receives the third message; and based on the first timestamp, the second timestamp, the third timestamp and the fourth timestamp, adjusting the offset and the frequency of the local clock, so that the current system time of the local clock is matched with the current system time of the main clock equipment. According to the invention, the technical problem that stable and high-precision clock synchronization is difficult to realize among distributed monitoring devices in an underground pipe gallery environment is solved.

The invention provides a nuclear power DCS system time calibration method and system, an electronic device and a medium, in the method, when a time calibration task is responded, whether a reference clock is forcibly calibrated or not is judged through local time and first calendar time of a dynamic clock, and the reference clock is forcibly calibrated without forcibly calibrating; the crystal oscillator error is quantized based on the second calendar time and the local time of the reference clock so as to capture the actual condition of the crystal oscillator deviation, then the dynamic clock timing rate is corrected by combining the first calendar time, the local time and the quantization parameter, and the obtained crystal oscillator deviation compensation parameter can dynamically adjust the dynamic clock timing rate instead of direct hopping timing. Time deviation caused by crystal oscillator errors is eliminated, the time reference of lower-level equipment can be effectively unified, and the problem of time errors caused by the crystal oscillator errors among the modules in the nuclear power DCS system is effectively solved.

The invention discloses a method for judging abnormal time jump. The method comprises the following steps: judging whether abnormal time jump occurs in a current time source or not; if the current time source is judged to have the abnormal time jump, acquiring a first timestamp of the current time source at the time when the abnormal time jump occurs and second timestamps of other time sources; wherein the other time sources are time sources except the current time source in the multiple time sources, and the first timestamp and the second timestamp are timestamps at the same moment; on the basis of the first timestamp, the second timestamp and a first preset time difference threshold value, the judgment of other time sources on the abnormal time jump is divided into credible jump judgment or uncredible jump judgment; and determining a final time abnormal jump judgment result according to the trusted jump judgment and the untrusted jump judgment. According to the invention, through multi-time-source cooperative verification, weight distribution and credibility grading evaluation mechanisms, in-vehicle system time errors can be avoided, and reliable guarantee is provided for driving safety.

The invention discloses a consistency voting method and device for multi-source time synchronization data, and relates to the technical field of high-reliability time synchronization of avionics, time sensitive networks and the like. The method comprises the following steps: respectively acquiring synchronous data including local capture time, original time deviation and cumulative frequency ratio from a plurality of independent clock sources to obtain corresponding clock source data; performing validity screening on the clock source data; extrapolating the original time deviation of each effective clock source to a set voting moment based on the cumulative frequency ratio to obtain a projection time deviation; based on all projection time deviations, determining an internally consistent credible clock source subset through bounded closure consistency verification; and according to the verification result and the redundancy condition, calculating and outputting system time correction or executing degradation output. According to the method, false deviation caused by asynchronous sampling can be eliminated, deterministic fault isolation and fault-tolerant voting are realized, and the output safety and reliability of the system in a high-safety-requirement scene are guaranteed.

The embodiment of the invention relates to the technical field of vehicles, and discloses a vehicle end time service method and device and a vehicle, and the method comprises the steps: judging whether the time difference between a standby clock source and a main clock source is within a preset range or not when the vehicle is switched from the standby clock source to the main clock source; if yes, switching to the master clock source as a system time source for timing, and outputting a timestamp message according to the master clock source; if not, the standby clock source serves as a system time source for timing, and timestamp messages output according to the standby clock source are accumulated or subtracted according to a preset step length, so that the timestamp messages are gradually close to the time of the main clock source until the time difference between the timestamp messages obtained through accumulation and the main clock source is within a preset range, and the time difference between the timestamp messages obtained through accumulation and the time difference between the timestamp messages obtained through accumulation and the time difference between the timestamp messages obtained through accumulation and the main clock source is within the preset range; the standby clock source comprises an RTC time component or an NTP time component, and the main clock source comprises a GNSS module. By applying the technical scheme of the invention, the problem of log function loss caused by time jump in the prior art can be solved.