148 results about "Register allocation" patented technology

The invention discloses an object routing node, a routing method and a network-on-chip. The object routing node comprises a first register and a second register, and the first register is configured to respond to the condition that a first message of a first type and a second message of a second type are received at the same time, select to store the first message and send the second message to the object routing node under the condition that a next routing node of the object routing node meets a scheduling condition. Providing the first message for a next routing node; the second register is configured to acquire the second message in response to the fact that the second message is not received by the first register and the anti-starvation mechanism is triggered, and the anti-starvation mechanism is configured to indicate that after the first register is vacant, the first register does not receive the first type of message until the second message is scheduled to the next routing node through the first register. According to the object routing node, the arbitration logic is reduced, and the resource overhead caused by the arbitration logic is greatly reduced.

The embodiment of the invention provides a register overflow optimization method and device and a storage medium, and is applied to the technical field of chips. In the method, for each virtual register in a target program, based on a physical register type supported by an instruction operand where the virtual register is located, the virtual register is optimized; selecting a corresponding target register class from N candidate register classes, wherein N is greater than 1; allocating a first physical register in the target register class to the virtual register; when register overflow occurs, a target register is selected from the allocated first physical registers, the instruction operand stored in the target register overflows to the second physical registers in the other N-1 candidate register classes, and compared with the mode that the instruction operand overflows to the memory to generate read-write operation on the memory, the instruction operand stored in the target register overflows to the second physical registers in the other N-1 candidate register classes; according to the method, different types of physical registers are overflowed, read-write operation aiming at the physical registers is generated, the pressure of the registers is relieved, the performance overhead of the overflowed memories is reduced, and the register distribution efficiency is improved.

The invention relates to the technical field of instruction set conversion, and discloses an instruction set conversion method of a GPU heterogeneous environment based on simulation software. According to the method, the key instruction stream in the simulation task is accurately captured through the dynamic instrumentation method, and a solid foundation is provided for subsequent processing; the method comprises the following steps: dividing an original instruction stream into a plurality of instruction blocks to be converted through a classification mechanism according to instruction semantic features and hardware suitability, and creating conditions for parallel conversion; a lightweight front-end translator is adopted to efficiently convert classified instruction blocks into architecture-independent intermediate representations, the degree of parallelism and the data dependency relationship between instructions are reserved, the intermediate representation instructions are deeply optimized, and the method comprises the key steps of instruction selection, register allocation, instruction recombination, SIMT mapping, instruction coding and the like. And generating a native instruction of the target GPU architecture through accelerated translation of the target GPU thread block. According to the method, the instruction conversion period is shortened, and the correctness and the execution efficiency of the conversion result are improved.

The invention discloses a data processing method, a multi-core heterogeneous system and a computer readable storage medium, and belongs to the technical field of data processing.The method comprises the steps that in the initialization stage of a hardware system, a physical storage space is allocated based on a predefined physical address boundary, and the physical storage space comprises a shared space; writing predefined configuration data corresponding to the shared space into a configuration register of the storage management module and latching the configuration register, wherein the configuration data comprises an access control strategy and a storage attribute; in the starting stage of the operating system, an address mapping relation is obtained, the address mapping relation comprises a target mapping relation, and under the condition that the operating system runs, a storage management module is triggered based on an instruction of a target operation to execute the target operation based on the address mapping relation, configuration data and a virtual address corresponding to the instruction, the target operation is read operation or write operation. The calculation amount of the processor is greatly reduced, and the time consumption for reading and writing data is reduced on the whole.

The application relates to a processor, component, device and method for filter processing of an IIR filter. The processor comprises a first configuration register, a second configuration register, a general register and a matrix multiplication accumulation unit. The general register sequentially reads and stores each row of coefficients of a coefficient matrix of each order of the IIR filter. The matrix multiplication accumulation unit obtains the same input element corresponding to the stored current row of coefficients when the first configuration register is configured in a broadcast mode, copies the stored current row of coefficients when the first configuration register is configured in a copy mode, multiplies the current row of coefficients with the corresponding input element in parallel to obtain corresponding products, and sequentially accumulates the product results of each row of coefficients to obtain a final output value, so that at least four output variables of sequential sampling moments are obtained each time. In this way, the time consumption of IIR filter operation can be significantly shortened, and sufficient acceleration effect is provided.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

The invention discloses a phase offset configuration method based on a device unique identifier RCA, and belongs to the technical field of storage device management. Comprising the following steps: S1, a host activates all connected eMMC equipment through a standard eMMC initialization command; s2, the host allocates a unique relative device address RCAi for each eMMC device; s3, the host counts the total number n of the currently active devices; s4, calculating a phase deviation angle delta phi i for each eMMC device based on the relative device address RCAi and the total number n of the devices; s5, the host writes the phase deviation angle delta phi i into an extension register of each eMMC device through an extension register configuration command; and S6, the host activates the phase deviation of the target device, and data transmission is carried out in a specified phase window, so that each eMMC device only drives the data bus in the exclusive time slot corresponding to the phase deviation angle delta phi i of the eMMC device. Through innovative combination of protocol layer dynamic configuration and physical layer time isolation, the problems of signal conflict, delay and power consumption in a multi-eMMC equipment system are thoroughly solved.

The application discloses a kind of compiler automatic debugging method and system for VLIW and SIMD architecture, the method of the application includes the semantic correctness verification for the program to be checked to judge whether the program to be checked exists semantic error relative to source program, if semantic correctness verification finds that there is semantic error, then determine that debugging is not passed, otherwise the physical register verification for the program to be checked to judge whether the program to be checked exists physical register allocation error, if there is physical register allocation error, then determine that debugging is not passed, otherwise determine that debugging is passed;When determining that debugging is not passed, then generate feedback verification report.The application can automatically check the semantic correctness of program in the process of compiling, and provide accurate verification report (including error occurrence position and type etc.) for developer, improve the efficiency of compiler development, reduce the burden of developer.

The invention relates to the field of integrated circuits and the field of chip debugging, and provides an efficient DDR4 memory debugging system and method for an SoC chip, and the system comprises a parameter debugging module which is used for adjusting to-be-adjusted parameters in a register configuration file according to DIMM information, the register configuration file and working mode information, after the register parameter configuration is completed, a DDR4 IP is started to execute a training task according to the training parameter setting and the training control setting; the test module is used for checking whether the adjusted register parameters are correct or not and monitoring whether the training result of the DDR4 IP for executing the training task is correct or not, performing read-write test on the DRAM, and selecting to start the operating system when it is determined that checking and training are passed and the read-write test is passed. The debugging error rate can be effectively reduced, the debugging progress is accelerated, and the debugging efficiency is improved.

The invention discloses a PCM (Pulse Code Modulation) collector dynamic framing IP core and method based on an FPGA (Field Programmable Gate Array). The IP core comprises a register access module, a DNA authorization module, an acquisition frame processing module, a framing control module and a PCM coding module. Comprising the following steps: performing parameter configuration on an IP core register; the DNA authorization module verifies the authorization key; the acquisition frame processing module receives and caches the acquisition frames in parallel and assembles PCM frame data; and performing PCM coding according to the code pattern configured by the register. The method has the beneficial effects that the frame format is high in universality, high in flexibility and high in deployment efficiency; predefinition and rapid dynamic switching of three frame formats are supported; parallel framing of 32 paths of acquisition frames is supported; common PCM code pattern output is supported; all functions can be accessed through a register, and extra logic is not needed; the register interface adopts a standard AXI-Lite interface; and a DNA authorization function is integrated.

The invention belongs to the technical field of hardware design, and provides a sharing operation method, system and equipment of a network acceleration unit and a medium, and the method comprises the step of configuring a shared general register, an exclusive general register and an exclusive special register group for multiple hosts in a single network acceleration unit. Each host accesses the register through the low-speed bus based on the unique identifier. And the acceleration unit performs data interaction with each host through a high-speed bus according to the configuration of the register. When the host operation is processed, the management message and the data transmission message are distinguished by judging whether the basic communication resource register group is accessed or not, and high-order modification and resource mapping are carried out on a load data address in the data transmission message. When an external data packet is received, a target host is determined through analysis and address matching, and resource identifier mapping and data access are carried out. According to the invention, each host is ensured to have independent communication resources and data channels, the complexity and the cost of hardware implementation are reduced, and the resource utilization rate and the system expansibility are improved.

A computer-implemented method for allocating registers for multi-core programs. The method includes generating core-specific programs for execution units of cores, wherein each program contains core-specific configurations. The method includes analyzing the core-specific programs to identify core-specific differences. The method includes creating a uniformized program that consolidates semantics of all programs for the execution units while retaining operations to account for core-specific differences. The method includes performing live range analysis of the uniformized program to identify active intervals for variables and creating segmented live ranges to partition the intervals into global and core-specific segments. The method includes allocating registers to the execution units using the segmented live ranges and multi-casting the uniformized program to the execution units of the cores.

The invention relates to a register resource allocation method, computer equipment, a readable storage medium and a program product. The method comprises the following steps: constructing a function group through a calling relationship between functions, wherein the function group comprises a coroutine kernel function and at least one coroutine subfunction; creating a resource record table corresponding to the function group, wherein the resource record table is used for recording register resources allocated to coroutine kernel functions and / or coroutine sub-functions in the function group; and carrying out register allocation on the coroutine kernel function and the coroutine sub-function in the function group based on the resource record table. By adopting the method, the requirements of local variable register resource isolation and shared variable register resource consistency in a collaborative mode can be met, so that the parallel computing efficiency is improved.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

The invention provides a programmable logic device dynamic register configuration device and a control method thereof. The configuration device for the dynamic register of the programmable logic device comprises an external controller used for providing a configuration instruction and configuration data; the main controller is used for receiving and analyzing the configuration data, generating a gating signal and recombining a data packet; at least one multiplexing module, each multiplexing module being configured to include a register block; and one or more stages of sub-controllers are arranged between the main controller and the multiplexing module and are used for further analyzing the data packet and controlling the target register group to complete read-write operation. In addition, the invention further provides a control method corresponding to the configuration device. Some embodiments of the invention aim to solve the problems of high configuration switching time consumption and uncertain configuration switching time in the prior art on the premise of not increasing too much complexity and area overhead.

The invention relates to an interrupt controller isolation access control method based on a virtual machine monitor, and the method comprises the steps: analyzing an access instruction of a virtual machine to an interrupt controller, so as to obtain an operation attribute and a target address; querying a predefined mapping relationship based on the virtual machine identifier, the processor core information and the target address, and generating an interrupt nucleophilicity parameter; dynamically generating a register operation mask according to the interrupt nucleophilicity parameter and interrupt register configuration information corresponding to the target address; verifying the access authority of the virtual machine to the target address based on the register operation mask; and in response to the fact that the access permission passes the verification, executing the access of the access instruction to the interrupt controller in an atomic operation mode by applying the register operation mask.

The application discloses a processor, a display card, a computer device, a register allocation method and device, and belongs to the technical field of register management. The processor comprises a plurality of registers, a register management unit and a task assembling unit. The register management unit is used for dividing the plurality of registers into at least one configuration block set, each configuration block set in the at least one configuration block set comprising at least one configuration block, and the at least one configuration block comprising at least two registers in the plurality of registers. The task assembling unit is used for allocating a first configuration block set to a first thread group, and the first configuration block set being one of the at least two configuration block sets. The processor allocates register resources in the form of configuration blocks, and can improve the allocation and release efficiency of register resources.

The present disclosure provides a register configuration system, method, and electronic device. The register configuration system includes a display processing unit, memory, and a hardware automatic control unit. The display processing unit includes multiple registers. The memory includes at least one pre-stored configuration instruction, wherein the configuration instruction is configured to indicate target registers that need to be configured in the display processing unit. The hardware automatic control unit is connected to a register configuration interface of the display processing unit. The hardware automatic control unit is configured to receive a startup command and, based on the startup command, retrieve and parse the configuration instructions from the memory. After parsing the configuration instructions, the hardware automatic control unit configures the target registers in the display processing unit. The startup command includes the storage address of the configuration instructions.

The invention discloses an SNN learning accelerator for ECG monitoring, which comprises a register configuration module, an asynchronous global control module, an asynchronous neural network control module, an asynchronous binary classification CNN module, an asynchronous quadruple classification SNN module, an asynchronous weight updating module and a memory management module, and is characterized in that firstly, a circuit corresponding to the accelerator constructs a double-layer dynamic network; layered dynamic power consumption management: selectively activating a high-precision secondary anomaly detection four-classification SNN network through a primary anomaly detection two-classification CNN network; secondly, the accelerator supports on-chip reasoning and efficient learning, and effectively eliminates ECG feature differences of different individuals on the premise of ensuring privacy security of user data; and finally, the circuit is controlled by using a pulse neural network and an asynchronous logic circuit, so that compared with a synchronous network, the power consumption is greatly reduced.

The invention provides a random instruction sequence generation method, a random instruction sequence generator and a random instruction sequence verification system. N instances are created according to microinstruction quantity parameters in a target test case; determining an instruction slot identifier and a target instruction library corresponding to each instance according to the number of instruction slots; determining a matching instruction of the instance according to the target instruction library; performing register allocation according to the matching instruction of each instance, and determining information of each register in the microinstruction corresponding to the instance to obtain a corresponding assembly instruction; and generating an assembly instruction file according to the sorting number corresponding to each instance and all the assembly instructions, wherein the assembly instruction file comprises a random instruction sequence formed by the assembly instructions according to the sorting numbers corresponding to the instances and an instruction slot identifier corresponding to each assembly instruction. A random instruction sequence matched with the processor of the ultra-long instruction word framework can be generated, various test scenes can be simulated and completed, and the method is used for verifying the processor of the ultra-long instruction word framework.

The embodiment of the specification provides a test method, which can be executed by a host computer and used for testing a message filtering function of a target controller in a device under test. When the method is implemented, current register information of the target controller is automatically acquired after a target test case is executed, and a target ID range is determined according to the register information. Then, based on test information such as the actual received message and the target ID range, the filtering function test is automatically completed. The method can automatically configure the controller through register configuration information in the test case, and automatically acquire the register state after the test, so that full-process automation is realized. This avoids errors, delays and interruptions that may be introduced by manual configuration, reading records and result checking, and significantly improves the continuity, efficiency and accuracy of the test process.

The invention discloses a phase-locked loop integrated structure and a lock loss detection method thereof, and belongs to the field of digital-analog hybrid integrated circuits. In the structure, an on-chip clock outputs an IRC clock to a clock switching selection circuit; the phase-locked loop receives an external clock, carries out frequency division and frequency multiplication, outputs a PLL output clock to the clock switching selection circuit, and outputs a PLL locking instruction at the same time. The register configuration module writes input frequency division parameters, outputs frequency division parameters and frequency multiplication parameters and configures the parameters to the phase-locked loop, writes the upper limit and the lower limit of expected PLL output clock frequency and configures the upper limit and the lower limit to the PLL clock exception control module, and sets a register bit field; the PLL clock abnormity control module outputs a LOCK signal to the clock switching selection circuit, counts an IRC clock and a PLL output clock, and performs CPU reset or interruption through a register bit field; and the clock switching selection circuit selects the IRC clock or the PLL to output the clock to the CPU through the LOCK signal. According to the invention, the problem that the output clock frequency range cannot be accurately detected when the PLL loses lock in the prior art can be solved.

The application discloses a DSP-oriented VLIW scheduling and packing method, which comprises the following steps: step 1, performing an LLVM IR optimization PASS sequence; step 2, constructing an instruction dependency graph (IDG); step 3, scheduling and packing before register allocation according to the global IDG; and step 4, reconstructing the IDG according to a register allocation result, and then scheduling and packing after the register allocation according to the reconstructed IDG. The application discloses a detailed IDG based on an SSA format, reveals potential parallelism between instructions, allows a compiler to identify opportunities for parallel execution at an earlier stage, avoids the parallelism loss problem introduced by the traditional method in the post-register allocation packing, and significantly improves the execution efficiency of a program on a DSP platform.

The invention provides a register allocation method and device, an instruction transmitting method and device and electronic equipment, and relates to the technical field of computer processors, the method comprises the steps that N allocated register groups are acquired, and each register group comprises at least one physical register; selecting a target physical register group from the N register groups according to a register distribution rule when responding to the existence of the target logic register for register distribution; and allocating the target physical register group to the target logical register. By selecting the corresponding physical register group according to the operation type of the target instruction, resource isolation and special path allocation of different function instructions are realized, register resource competition is effectively avoided, a data path is optimized, access delay and power consumption are reduced, and the parallel execution efficiency, the function module utilization rate and the overall performance of a processor are improved.

The invention belongs to the field of hardware circuit design, and relates to a universal FLASH control method and system based on an AHB bus and a controller. The method comprises the following steps: configuring a bit width mode of the FLASH controller; configuring registers, wherein the registers comprise a time parameter register and an EDAC control register; obtaining an access request, an external bit width mode and a register configuration state of the AHB; adjusting an internal state mode according to the access request of the AHB and the configuration state of the register, and outputting a time sequence diagram; and executing corresponding operation according to the internal state mode, the external bit width mode and the access request of the AHB. On the basis of the transmission characteristics of the AHB bus, an off-chip universal NOR FLASH controller with a fault-tolerant mechanism is realized, and the controller can be compatible with different NOR FLASH devices.

The present application belongs to the technical field of heterogeneous processor machine code compilation, and particularly relates to a multi-task parallel heterogeneous processor machine code compilation generation method. The method comprises the following steps: defining a loadable heterogeneous task format based on a protobuf protocol and defining a device task format in a self-defined manner to describe binary machine code for task execution; parsing a model compiled by an MLIR compiler through an MLIR parsing module to extract model structure, weight parameters and task dependency compilation information required for processing unit execution; mapping and generating a binary file containing complete register configuration for describing task execution through processing of an MLIR compiler backend; and constructing a task dependency graph based on the producer-consumer dependency relationship between tasks. The present application realizes multi-task parallel scheduling and resource optimization, thereby reducing redundant occupation of computing resources.

The application provides a demultiplexing method, device, GPIO module, electronic equipment and storage medium. The demultiplexing method comprises: receiving a function name of a function to be demultiplexed; demultiplexing the function corresponding to the function name based on a preset demultiplexing array, the preset demultiplexing array comprising a function name, a register address and a demultiplexing register configuration value and a corresponding relationship among the three, the demultiplexing being used to configure the register address corresponding to a pin based on the demultiplexing register configuration value corresponding to the function name, so that the pin realizes the function corresponding to the function name. Through the above demultiplexing method, the demultiplexing of the chip pin function can be realized only by receiving the function name, so that the demultiplexing related operation becomes quite simple, and the efficiency and accuracy of the demultiplexing are effectively improved.

The invention relates to the field of compiler optimization, and provides a register allocation method, which comprises the following steps of: firstly, reversely scanning a control flow diagram, and constructing an active range table for all variables so as to accurately record a dead interval of each variable; secondly, carrying out dead interval matching and multiplexing operation in a register allocation process; and finally, carrying out weight calculation by combining variable active range and dead interval features, and optimizing an overflow decision. The invention aims to realize register multiplexing by identifying and utilizing the dead interval in the variable active range, thereby improving the utilization rate of the register, reducing the overflow of the register and improving the execution performance of the program.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.

The invention discloses a complex SoC time sequence optimization-oriented register structure and a design method, and belongs to the field of super-large-scale digital integrated circuits, the design method comprises the following steps: a user register configuration interface unit and a system memory data flow control unit are respectively and correspondingly provided with a set of independent CPU host interfaces; performing frequency division processing on the system clock signal to obtain a register configuration clock signal, wherein the register configuration clock signal is a low-frequency clock; based on a register configuration clock signal, the user register configuration interface unit performs data read-out operation to obtain read-out data and returns the read-out data to a corresponding CPU host interface, and data write-in operation of all function configuration bits of the user register configuration interface unit is copied to a corresponding function control logic unit; and each function configuration bit completes the control logic of the corresponding function under a system clock signal after signal synchronization. According to the invention, the time sequence problems of signal crossing, wiring congestion and the like in the multifunctional configuration register in the complex SoC can be solved.