95 results about "Register allocation" patented technology

The invention relates to the technical field of instruction set conversion, and discloses an instruction set conversion method of a GPU heterogeneous environment based on simulation software. According to the method, the key instruction stream in the simulation task is accurately captured through the dynamic instrumentation method, and a solid foundation is provided for subsequent processing; the method comprises the following steps: dividing an original instruction stream into a plurality of instruction blocks to be converted through a classification mechanism according to instruction semantic features and hardware suitability, and creating conditions for parallel conversion; a lightweight front-end translator is adopted to efficiently convert classified instruction blocks into architecture-independent intermediate representations, the degree of parallelism and the data dependency relationship between instructions are reserved, the intermediate representation instructions are deeply optimized, and the method comprises the key steps of instruction selection, register allocation, instruction recombination, SIMT mapping, instruction coding and the like. And generating a native instruction of the target GPU architecture through accelerated translation of the target GPU thread block. According to the method, the instruction conversion period is shortened, and the correctness and the execution efficiency of the conversion result are improved.

The invention discloses a data processing method, a multi-core heterogeneous system and a computer readable storage medium, and belongs to the technical field of data processing.The method comprises the steps that in the initialization stage of a hardware system, a physical storage space is allocated based on a predefined physical address boundary, and the physical storage space comprises a shared space; writing predefined configuration data corresponding to the shared space into a configuration register of the storage management module and latching the configuration register, wherein the configuration data comprises an access control strategy and a storage attribute; in the starting stage of the operating system, an address mapping relation is obtained, the address mapping relation comprises a target mapping relation, and under the condition that the operating system runs, a storage management module is triggered based on an instruction of a target operation to execute the target operation based on the address mapping relation, configuration data and a virtual address corresponding to the instruction, the target operation is read operation or write operation. The calculation amount of the processor is greatly reduced, and the time consumption for reading and writing data is reduced on the whole.

The application relates to a processor, component, device and method for filter processing of an IIR filter. The processor comprises a first configuration register, a second configuration register, a general register and a matrix multiplication accumulation unit. The general register sequentially reads and stores each row of coefficients of a coefficient matrix of each order of the IIR filter. The matrix multiplication accumulation unit obtains the same input element corresponding to the stored current row of coefficients when the first configuration register is configured in a broadcast mode, copies the stored current row of coefficients when the first configuration register is configured in a copy mode, multiplies the current row of coefficients with the corresponding input element in parallel to obtain corresponding products, and sequentially accumulates the product results of each row of coefficients to obtain a final output value, so that at least four output variables of sequential sampling moments are obtained each time. In this way, the time consumption of IIR filter operation can be significantly shortened, and sufficient acceleration effect is provided.

The invention discloses a phase offset configuration method based on a device unique identifier RCA, and belongs to the technical field of storage device management. Comprising the following steps: S1, a host activates all connected eMMC equipment through a standard eMMC initialization command; s2, the host allocates a unique relative device address RCAi for each eMMC device; s3, the host counts the total number n of the currently active devices; s4, calculating a phase deviation angle delta phi i for each eMMC device based on the relative device address RCAi and the total number n of the devices; s5, the host writes the phase deviation angle delta phi i into an extension register of each eMMC device through an extension register configuration command; and S6, the host activates the phase deviation of the target device, and data transmission is carried out in a specified phase window, so that each eMMC device only drives the data bus in the exclusive time slot corresponding to the phase deviation angle delta phi i of the eMMC device. Through innovative combination of protocol layer dynamic configuration and physical layer time isolation, the problems of signal conflict, delay and power consumption in a multi-eMMC equipment system are thoroughly solved.

The application discloses a kind of compiler automatic debugging method and system for VLIW and SIMD architecture, the method of the application includes the semantic correctness verification for the program to be checked to judge whether the program to be checked exists semantic error relative to source program, if semantic correctness verification finds that there is semantic error, then determine that debugging is not passed, otherwise the physical register verification for the program to be checked to judge whether the program to be checked exists physical register allocation error, if there is physical register allocation error, then determine that debugging is not passed, otherwise determine that debugging is passed;When determining that debugging is not passed, then generate feedback verification report.The application can automatically check the semantic correctness of program in the process of compiling, and provide accurate verification report (including error occurrence position and type etc.) for developer, improve the efficiency of compiler development, reduce the burden of developer.

The invention relates to the field of integrated circuits and the field of chip debugging, and provides an efficient DDR4 memory debugging system and method for an SoC chip, and the system comprises a parameter debugging module which is used for adjusting to-be-adjusted parameters in a register configuration file according to DIMM information, the register configuration file and working mode information, after the register parameter configuration is completed, a DDR4 IP is started to execute a training task according to the training parameter setting and the training control setting; the test module is used for checking whether the adjusted register parameters are correct or not and monitoring whether the training result of the DDR4 IP for executing the training task is correct or not, performing read-write test on the DRAM, and selecting to start the operating system when it is determined that checking and training are passed and the read-write test is passed. The debugging error rate can be effectively reduced, the debugging progress is accelerated, and the debugging efficiency is improved.

The invention belongs to the technical field of hardware design, and provides a sharing operation method, system and equipment of a network acceleration unit and a medium, and the method comprises the step of configuring a shared general register, an exclusive general register and an exclusive special register group for multiple hosts in a single network acceleration unit. Each host accesses the register through the low-speed bus based on the unique identifier. And the acceleration unit performs data interaction with each host through a high-speed bus according to the configuration of the register. When the host operation is processed, the management message and the data transmission message are distinguished by judging whether the basic communication resource register group is accessed or not, and high-order modification and resource mapping are carried out on a load data address in the data transmission message. When an external data packet is received, a target host is determined through analysis and address matching, and resource identifier mapping and data access are carried out. According to the invention, each host is ensured to have independent communication resources and data channels, the complexity and the cost of hardware implementation are reduced, and the resource utilization rate and the system expansibility are improved.

A computer-implemented method for allocating registers for multi-core programs. The method includes generating core-specific programs for execution units of cores, wherein each program contains core-specific configurations. The method includes analyzing the core-specific programs to identify core-specific differences. The method includes creating a uniformized program that consolidates semantics of all programs for the execution units while retaining operations to account for core-specific differences. The method includes performing live range analysis of the uniformized program to identify active intervals for variables and creating segmented live ranges to partition the intervals into global and core-specific segments. The method includes allocating registers to the execution units using the segmented live ranges and multi-casting the uniformized program to the execution units of the cores.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

The invention provides a programmable logic device dynamic register configuration device and a control method thereof. The configuration device for the dynamic register of the programmable logic device comprises an external controller used for providing a configuration instruction and configuration data; the main controller is used for receiving and analyzing the configuration data, generating a gating signal and recombining a data packet; at least one multiplexing module, each multiplexing module being configured to include a register block; and one or more stages of sub-controllers are arranged between the main controller and the multiplexing module and are used for further analyzing the data packet and controlling the target register group to complete read-write operation. In addition, the invention further provides a control method corresponding to the configuration device. Some embodiments of the invention aim to solve the problems of high configuration switching time consumption and uncertain configuration switching time in the prior art on the premise of not increasing too much complexity and area overhead.

The invention relates to an interrupt controller isolation access control method based on a virtual machine monitor, and the method comprises the steps: analyzing an access instruction of a virtual machine to an interrupt controller, so as to obtain an operation attribute and a target address; querying a predefined mapping relationship based on the virtual machine identifier, the processor core information and the target address, and generating an interrupt nucleophilicity parameter; dynamically generating a register operation mask according to the interrupt nucleophilicity parameter and interrupt register configuration information corresponding to the target address; verifying the access authority of the virtual machine to the target address based on the register operation mask; and in response to the fact that the access permission passes the verification, executing the access of the access instruction to the interrupt controller in an atomic operation mode by applying the register operation mask.

The application discloses a processor, a display card, a computer device, a register allocation method and device, and belongs to the technical field of register management. The processor comprises a plurality of registers, a register management unit and a task assembling unit. The register management unit is used for dividing the plurality of registers into at least one configuration block set, each configuration block set in the at least one configuration block set comprising at least one configuration block, and the at least one configuration block comprising at least two registers in the plurality of registers. The task assembling unit is used for allocating a first configuration block set to a first thread group, and the first configuration block set being one of the at least two configuration block sets. The processor allocates register resources in the form of configuration blocks, and can improve the allocation and release efficiency of register resources.

The present disclosure provides a register configuration system, method, and electronic device. The register configuration system includes a display processing unit, memory, and a hardware automatic control unit. The display processing unit includes multiple registers. The memory includes at least one pre-stored configuration instruction, wherein the configuration instruction is configured to indicate target registers that need to be configured in the display processing unit. The hardware automatic control unit is connected to a register configuration interface of the display processing unit. The hardware automatic control unit is configured to receive a startup command and, based on the startup command, retrieve and parse the configuration instructions from the memory. After parsing the configuration instructions, the hardware automatic control unit configures the target registers in the display processing unit. The startup command includes the storage address of the configuration instructions.

The embodiment of the specification provides a test method, which can be executed by a host computer and used for testing a message filtering function of a target controller in a device under test. When the method is implemented, current register information of the target controller is automatically acquired after a target test case is executed, and a target ID range is determined according to the register information. Then, based on test information such as the actual received message and the target ID range, the filtering function test is automatically completed. The method can automatically configure the controller through register configuration information in the test case, and automatically acquire the register state after the test, so that full-process automation is realized. This avoids errors, delays and interruptions that may be introduced by manual configuration, reading records and result checking, and significantly improves the continuity, efficiency and accuracy of the test process.

The present application belongs to the technical field of heterogeneous processor machine code compilation, and particularly relates to a multi-task parallel heterogeneous processor machine code compilation generation method. The method comprises the following steps: defining a loadable heterogeneous task format based on a protobuf protocol and defining a device task format in a self-defined manner to describe binary machine code for task execution; parsing a model compiled by an MLIR compiler through an MLIR parsing module to extract model structure, weight parameters and task dependency compilation information required for processing unit execution; mapping and generating a binary file containing complete register configuration for describing task execution through processing of an MLIR compiler backend; and constructing a task dependency graph based on the producer-consumer dependency relationship between tasks. The present application realizes multi-task parallel scheduling and resource optimization, thereby reducing redundant occupation of computing resources.

The application provides a demultiplexing method, device, GPIO module, electronic equipment and storage medium. The demultiplexing method comprises: receiving a function name of a function to be demultiplexed; demultiplexing the function corresponding to the function name based on a preset demultiplexing array, the preset demultiplexing array comprising a function name, a register address and a demultiplexing register configuration value and a corresponding relationship among the three, the demultiplexing being used to configure the register address corresponding to a pin based on the demultiplexing register configuration value corresponding to the function name, so that the pin realizes the function corresponding to the function name. Through the above demultiplexing method, the demultiplexing of the chip pin function can be realized only by receiving the function name, so that the demultiplexing related operation becomes quite simple, and the efficiency and accuracy of the demultiplexing are effectively improved.

The invention relates to the field of compiler optimization, and provides a register allocation method, which comprises the following steps of: firstly, reversely scanning a control flow diagram, and constructing an active range table for all variables so as to accurately record a dead interval of each variable; secondly, carrying out dead interval matching and multiplexing operation in a register allocation process; and finally, carrying out weight calculation by combining variable active range and dead interval features, and optimizing an overflow decision. The invention aims to realize register multiplexing by identifying and utilizing the dead interval in the variable active range, thereby improving the utilization rate of the register, reducing the overflow of the register and improving the execution performance of the program.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.

The embodiment of the invention discloses a software and hardware collaborative dynamic voltage frequency adjustment method and electronic equipment, and the method comprises the steps: carrying out the parameter initialization operation of a register block, obtaining a register configuration parameter, carrying out the initialization of an adjustment parameter based on the register configuration parameter, obtaining a target adjustment parameter, generating an operation completion flag instruction, and carrying out the operation completion flag instruction. The operation completion mark instruction is sent to the adjusting module, when the adjusting module responds to the operation completion mark instruction, the register configuration parameters and the target adjusting parameters are written into the register set, and the adjusting state of the adjusting module is converted based on the register configuration parameters. In the adjusting state, the trigger state of the counting flag bit and the soft error flag bit is determined, the corresponding adjusting strategy is determined based on the trigger state, and the voltage or frequency is adjusted according to the adjusting strategy, so that the software control end can configure the adjusting standard matched with the hardware control end according to the actual requirement of the system; therefore, the flexibility and accuracy of system adjustment are improved.

The invention provides a parameter configuration method and device of an external decoder, the external decoder and a storage medium. The method comprises the following steps: acquiring a network state of a network where the external decoder is located, load information of the external decoder and a user experience quality index; determining a target sampling rate of the external decoder based on the network state, the load information and the user experience quality index; matching from a parameter preset database based on the target sampling rate and the model of the external decoder to obtain target register configuration information; the external decoder is configured based on the target register configuration information, and the target sampling rate is determined by obtaining the network state, the load information and the user experience quality index, so that the processing parameters of the external decoder are dynamically adjusted, and the high-quality audio service can be provided.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data valu

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

Embodiments of the present application provide a register overflow optimization method and device and a storage medium, applied to the chip technical field, in the method, for each virtual register in a target program, based on the physical register type supported by the instruction operand where the virtual register is located, a corresponding target register class is selected from N candidate register classes, N is greater than 1; a first physical register in the target register class is allocated to the virtual register; when a register overflow occurs, a target register is selected from the allocated multiple first physical registers, and the instruction operand saved in the target register is overflowed to a second physical register in the other N-1 candidate register classes. Compared with overflowing the instruction operand to the memory to generate read and write operations on the memory, the present application overflows to different types of physical registers, generates read and write operations on the physical registers, relieves the pressure of the registers, reduces the performance overhead of overflowing to the memory, and improves the register allocation efficiency.

The application relates to the field of register allocation of a compiler, in particular to a register selection method based on a bit vector and a configurable mapping. The method comprises the following steps: obtaining a category mask corresponding to a target constraint and an availability bit vector; each bit in the availability bit vector corresponds to a register; if 0 in the availability bit vector represents an idle corresponding register and 1 represents an occupied corresponding register, then performing a NOT operation on the availability bit vector, performing a bitwise AND operation on the vector obtained after the NOT operation and the category mask corresponding to the target constraint, and obtaining a vector obtained after the bitwise AND operation; and performing a first position bit detection on the vector obtained after the bitwise AND operation, and determining a register corresponding to a first value 1 bit number obtained after the detection as a selected idle register satisfying the target constraint. The application can improve register category filtering efficiency and reduce the determination cost of register availability.

This invention relates to the field of computer technology and provides a method and apparatus for cross-function vector register collaborative allocation for RISC-V vector extensions. The method includes: performing cross-function data flow analysis on the program to identify active vector registers and construct an active information set; establishing LMUL constraint propagation relationships based on this and determining the target LMUL configuration; performing collaborative vector register allocation between the caller and callee based on the active information set and the target LMUL configuration, and establishing a register mapping relationship; performing overflow optimization based on vector characteristics for vector data that cannot be retained; and collaboratively maintaining the vector execution context at function call boundaries. This invention can reduce register reallocation and overflow overhead during cross-function calls, reduce memory access pressure, and improve RISC-V vector register resource utilization and program execution efficiency.

This application relates to the field of compilers, and in particular to a method for dynamically allocating caller-saved register storage space. Applied to the register allocation stage, it includes the following steps: obtaining the set of caller-saved registers that need to be saved at the current call point; obtaining the required storage space size N for the current call point based on the set of caller-saved registers; allocating a contiguous storage space of size N for this call by adjusting the stack pointer before generating the save instruction; writing the values ​​of the caller-saved registers that need to be saved at the current call point into the contiguous storage space of size N; executing the function call instruction; after the function call returns, restoring the values ​​of each caller-saved register written in the contiguous storage space of size N to the corresponding caller-saved register; and restoring the stack pointer to release the contiguous storage space of size N. This invention can solve the problems of stack space waste, high complexity, and susceptibility to errors.

Reducing the range of activity of variables of register allocation for a structured control flow program is provided. The method includes defining an affine expression for each static single assignment SSA variable contained in an input program of a computer compiler. The affine expression of the SSA variable in the input program is derived by replacing the affine expression of the input operand involved in the calculation of the SSA variable. The method defines dependency edges between nodes representing SSA variables in the dependency graph, where sources and destinations of the dependency edges represent definitions and uses of the SSA variables. The method identifies, among the dependent edges, one or more overlapping dependent edges having the same source, and eliminates longer ones of the overlapping dependent edges according to the derived affine expression.

The invention provides a dynamic register allocation method and system based on an RISC-V architecture, and belongs to the technical field of computers. The method comprises the steps that task characteristic data are received in real time; predicting a register demand corresponding to the task based on the task characteristic data; determining a partition decision of a self physical register based on the register demand; and dividing the register based on the partition decision, controlling the partition control register to dynamically configure the physical address range and the access authority of each physical register partition, and controlling the physical memory protection unit to configure the access rule of each physical register partition. According to the invention, the register demand is predicted based on the task characteristic data, the register is partitioned based on the register demand, and the dynamic allocation of the register is realized by expanding the type of the control and state register and the function of the physical memory protection unit, so that the allocation of the register adapts to the dynamic change of the task load during operation; and resource waste or conflict is avoided.

Systems and methods to perform per-register bin packing are disclosed. A system may include a memory and one or more processors coupled to the memory. The one or more processors may determine a first live range of a first variable in a source code and a second live range of a second variable in the source code. The first live range and the second live range may overlap in time during execution of an output code. The one or more processors may generate the output code including a first instruction for the first variable and a second instruction for the second variable. The first instruction may include a first register identifier, a first mask, and a first offset. The second instruction may include the first register identifier, a second mask, and a second offset.

The invention relates to the technical field of processors, in particular to a tile block instruction set architecture and a processing method, and the tile block instruction set architecture comprises a tile block parallel processing system control instruction, a tile block descriptor register configuration instruction, a tile block data handling instruction, a tile block data copying instruction and a tile block arithmetic instruction. According to the tile block instruction set architecture processing method, one or more tile block operation units, one or more tile block storage management units and one or more tile block calculation task scheduling and synchronization units are combined into a tile block parallel processing system, so that tile block instructions are allowed to be processed in parallel, and tile block-based data operation is completed. The architecture aims at solving the problems that when an existing processing system processes two-dimensional data blocks, instruction overhead is too large, data abstraction is insufficient, and the coupling degree of software and hardware is too high.