Debug system having assembler correcting register allocation errors

Inactive Publication Date: 2005-09-22
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

While the ability to use virtual names provides certain advantages, such as ease of use, register bank conflict issues may become more of an issue.
A further issue t

Method used

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  • Debug system having assembler correcting register allocation errors
  • Debug system having assembler correcting register allocation errors
  • Debug system having assembler correcting register allocation errors

Examples

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Embodiment Construction

[0027] Referring to FIG. 1, a system 10 includes a processor 12 coupled to one or more I / O devices, for example, network devices 14 and 16, as well as a memory system 18. The processor 12 includes multiple processors (“microengines” or “MEs”) 20, each with multiple hardware controlled execution threads 22. In the example shown, there are “n” microengines 20, and each of the microengines 20 is capable of processing multiple threads 22, as will be described more fully below. In the described embodiment, the maximum number “N” of threads supported by the hardware is eight. Each of the microengines 20 is connected to and can communicate with adjacent microengines.

[0028] In one embodiment, the processor 12 also includes a processor 24 that assists in loading microcode control for the microengines 20 and other resources of the processor 12, and performs other general-purpose computer type functions such as handling protocols and exceptions. In network processing applications, the process...

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Abstract

An assembler, which can be provided as part of a debugger and/or development system, avoids register allocation errors, such as register bank conflicts and/or insufficient physical registers, automatically.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] Not Applicable. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH [0002] Not Applicable. FIELD OF THE INVENTION [0003] The present invention relates generally to programming devices and, more particularly, to assembling source code to generate machine code. BACKGROUND OF THE INVENTION [0004] As is known in the art, some processors have multiple register banks from which operands are fed to a processing unit that performs a designated operation, e.g., shift, add, subtract etc. A first bank of registers provides operands to one port of the processing unit and the second bank of registers provide operands to a second port of the processing unit. While this arrangement has certain advantages, operands for a given instruction cannot come from the same bank of registers. [0005] In some known assemblers, the programmer typically writes instructions using physical register names (e.g. RO) rather than virtual names (e.g., num_packets), so that re...

Claims

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F11/3624
Inventor GUILFORD, JAMES D.
Owner INTEL CORP
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