37 results about "Register assignment" patented technology

A computer-implemented method for allocating registers for multi-core programs. The method includes generating core-specific programs for execution units of cores, wherein each program contains core-specific configurations. The method includes analyzing the core-specific programs to identify core-specific differences. The method includes creating a uniformized program that consolidates semantics of all programs for the execution units while retaining operations to account for core-specific differences. The method includes performing live range analysis of the uniformized program to identify active intervals for variables and creating segmented live ranges to partition the intervals into global and core-specific segments. The method includes allocating registers to the execution units using the segmented live ranges and multi-casting the uniformized program to the execution units of the cores.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

An apparatus and method for eliminating load instruction execution. For example, one embodiment includes: circuitry to track execution of a plurality of load instructions and responsively update tracking tables; allocation circuitry to allocate a first source register to an instance of the first load instruction and to identify locations of the corresponding data elements in the cache line based on the tracking tables; execution circuitry to load data corresponding to the instance of the first load instruction from the cache line and to load the data elements corresponding to instances of the subsequent load instructions to the same source register; the allocation circuitry to indicate the first source register to the instances of the subsequent load instructions and respective locations of the data elements in the first source register, the instances of the subsequent load instructions to move the respective data elements from the first source register to destination registers.

The invention relates to the field of compiler optimization, and provides a register allocation method, which comprises the following steps of: firstly, reversely scanning a control flow diagram, and constructing an active range table for all variables so as to accurately record a dead interval of each variable; secondly, carrying out dead interval matching and multiplexing operation in a register allocation process; and finally, carrying out weight calculation by combining variable active range and dead interval features, and optimizing an overflow decision. The invention aims to realize register multiplexing by identifying and utilizing the dead interval in the variable active range, thereby improving the utilization rate of the register, reducing the overflow of the register and improving the execution performance of the program.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data valu

Embodiments of the present application provide a register overflow optimization method and device and a storage medium, applied to the chip technical field, in the method, for each virtual register in a target program, based on the physical register type supported by the instruction operand where the virtual register is located, a corresponding target register class is selected from N candidate register classes, N is greater than 1; a first physical register in the target register class is allocated to the virtual register; when a register overflow occurs, a target register is selected from the allocated multiple first physical registers, and the instruction operand saved in the target register is overflowed to a second physical register in the other N-1 candidate register classes. Compared with overflowing the instruction operand to the memory to generate read and write operations on the memory, the present application overflows to different types of physical registers, generates read and write operations on the physical registers, relieves the pressure of the registers, reduces the performance overhead of overflowing to the memory, and improves the register allocation efficiency.

The application relates to the field of register allocation of a compiler, in particular to a register selection method based on a bit vector and a configurable mapping. The method comprises the following steps: obtaining a category mask corresponding to a target constraint and an availability bit vector; each bit in the availability bit vector corresponds to a register; if 0 in the availability bit vector represents an idle corresponding register and 1 represents an occupied corresponding register, then performing a NOT operation on the availability bit vector, performing a bitwise AND operation on the vector obtained after the NOT operation and the category mask corresponding to the target constraint, and obtaining a vector obtained after the bitwise AND operation; and performing a first position bit detection on the vector obtained after the bitwise AND operation, and determining a register corresponding to a first value 1 bit number obtained after the detection as a selected idle register satisfying the target constraint. The application can improve register category filtering efficiency and reduce the determination cost of register availability.

This application relates to the field of compilers, and in particular to a method for dynamically allocating caller-saved register storage space. Applied to the register allocation stage, it includes the following steps: obtaining the set of caller-saved registers that need to be saved at the current call point; obtaining the required storage space size N for the current call point based on the set of caller-saved registers; allocating a contiguous storage space of size N for this call by adjusting the stack pointer before generating the save instruction; writing the values ​​of the caller-saved registers that need to be saved at the current call point into the contiguous storage space of size N; executing the function call instruction; after the function call returns, restoring the values ​​of each caller-saved register written in the contiguous storage space of size N to the corresponding caller-saved register; and restoring the stack pointer to release the contiguous storage space of size N. This invention can solve the problems of stack space waste, high complexity, and susceptibility to errors.

Reducing the range of activity of variables of register allocation for a structured control flow program is provided. The method includes defining an affine expression for each static single assignment SSA variable contained in an input program of a computer compiler. The affine expression of the SSA variable in the input program is derived by replacing the affine expression of the input operand involved in the calculation of the SSA variable. The method defines dependency edges between nodes representing SSA variables in the dependency graph, where sources and destinations of the dependency edges represent definitions and uses of the SSA variables. The method identifies, among the dependent edges, one or more overlapping dependent edges having the same source, and eliminates longer ones of the overlapping dependent edges according to the derived affine expression.

The invention provides a dynamic register allocation method and system based on an RISC-V architecture, and belongs to the technical field of computers. The method comprises the steps that task characteristic data are received in real time; predicting a register demand corresponding to the task based on the task characteristic data; determining a partition decision of a self physical register based on the register demand; and dividing the register based on the partition decision, controlling the partition control register to dynamically configure the physical address range and the access authority of each physical register partition, and controlling the physical memory protection unit to configure the access rule of each physical register partition. According to the invention, the register demand is predicted based on the task characteristic data, the register is partitioned based on the register demand, and the dynamic allocation of the register is realized by expanding the type of the control and state register and the function of the physical memory protection unit, so that the allocation of the register adapts to the dynamic change of the task load during operation; and resource waste or conflict is avoided.

The invention discloses a register allocation method and device, a computer program product and a readable storage medium, belongs to the field of program compiling, is used for allocating registers for variables during program compiling, and solves the problem that registers cannot be allocated to a large number of variables in a program. Considering that if a node of which the degree is greater than the total number of registers exists in the conflict graph, part of neighbor nodes of the node need to be overflowed to a memory; the neighborhood node area (the node and the adjacent nodes thereof) of one node has divisibility; the method comprises the following steps: determining a target node of which the degree is greater than the total number of registers in a conflict graph, dividing a neighborhood node region of the target node into a plurality of node sub-regions, and meeting the following conditions: each node sub-region comprises the target node, and the degree of the target node in the node sub-region is less than the total number of registers; therefore, the situation that part of neighbor nodes of the target node cannot be allocated to the register and are overflowed to the memory is avoided, and the running efficiency of the executable program obtained through final compiling can be improved.

The application provides a random instruction sequence generation method, a generator and a verification system. N instances are created according to a microinstruction quantity parameter in a target test case. Instruction slot identifiers and a target instruction library corresponding to each instance are determined according to an instruction slot quantity. Matching instructions of the instances are determined according to the target instruction library. Register allocation is performed according to the matching instructions of each instance, each register information in the microinstruction corresponding to the instance is determined, and corresponding assembly instructions are obtained. An assembly instruction file is generated according to the sorting number corresponding to each instance and all the assembly instructions. The assembly instruction file comprises a random instruction sequence composed of the assembly instructions according to the sorting number corresponding to the instance and the instruction slot identifier corresponding to each assembly instruction. The random instruction sequence matched with a very long instruction word architecture processor can be generated, various test scenes can be simulated, and the verification of the very long instruction word architecture processor can be completed.

The application discloses a processor supporting register release, a register release method, a display card and equipment, and belongs to the technical field of register management. The processor comprises a plurality of registers, an allocation management unit and a resource management unit. The allocation management unit is used for allocating at least two register sets for a first thread group, and each register set in the at least two register sets comprises at least one register in the plurality of registers. The resource management unit is used for releasing a first register set in response to the end of use of all registers in the first register set by the first thread group, and the first register set is one register set in the at least two register sets. The processor supports early release of the first register set when the first thread group ends the use of all registers in the first register set, thereby avoiding the problem of low utilization of register resources caused by long-term occupation of the first register set by the first thread group.

Reducing live range of variables for register allocation of structured control-flow programs is provided. The method comprises defining an affine expression for each static single assignment (SSA) variable contained in an input program for a computer compiler. The affine expression of a SSA variable in the input program is derived by substitution of affine expressions of input operands involved in computation of the SSA variable. The method defines dependence edges between nodes representing the SSA variables in a dependence graph, wherein source and destination of dependence edges represent definition and use of the SSA variables. The method identifies one or more overlapping dependence edges with a same source among the dependence edges and eliminates the longer of the overlapping dependence edges according to the derived affine expressions.

The present disclosure relates to the technical field of processors. Provided are a processor structure based on odd-even scheduling and allocation, and a chip and an electronic device. In the processor structure based on odd-even scheduling and allocation provided in the present disclosure, a free physical register file is divided into an odd part and an even part in a renaming phase, and whether an odd physical register or an even physical register is allocated for the current renaming operation is determined according to an instruction type. The embodiments provided by the present disclosure can reduce by half the number of write ports of a register file, and can effectively perform the allocation and instruction scheduling of physical registers in combination with a register allocation balancing algorithm.

The invention relates to an electronic control firmware performance optimization method and related equipment, and the method comprises the following steps: carrying out the static semantic analysis of an original firmware code, and obtaining a firmware code symbol table; performing data stream tracking on the original firmware code based on the firmware code symbol table to obtain a data dependency graph; performing control flow sensitive analysis on the original firmware code based on the data dependency graph to obtain a control flow sensitive instruction sequence; performing loop expansion optimization on the control flow sensitive instruction sequence through an instruction scheduling engine technology to obtain an expanded instruction sequence; and performing register allocation on the original firmware code based on the expanded instruction sequence so as to reduce memory access times, improve the execution efficiency of the original firmware code, and solve the problems that traditional firmware development focuses on function implementation, neglects efficient matching between a code execution path and hardware resources, and improves the execution efficiency of the original firmware code. And the technical problem that instruction execution is delayed in a complex application scene is solved.

The application discloses a register allocation method, device, computer program product and readable storage medium, belongs to the field of program compilation, and is used for allocating registers for variables during program compilation, and solves the problem that a large number of variables in a program cannot be allocated registers; considering that if there is a node with a degree greater than the total number of registers in a conflict graph, part of neighbor nodes of the node need to be overflowed to a memory; and a neighbor node area (a node and adjacent nodes) of a node has divisibility; the application determines a target node with a degree greater than the total number of registers in the conflict graph, divides the neighbor node area of the target node into a plurality of node sub-areas, and meets that the node sub-areas all include the target node, and the degree of the target node in the node sub-areas is less than the total number of registers, so that part of neighbor nodes of the target node cannot be allocated to registers and are overflowed to the memory, and the running efficiency of an executable program obtained through final compilation is improved.

This invention relates to a method for parallel optimization of micro-matrix operations at the instruction level based on heterogeneous many-core processor systems, belonging to the technical field of electronic information. The method includes: Step 1: A particle-first linear address mapping architecture; mapping the multidimensional tensor space in the physics problem to the one-dimensional linear physical address space of the GPU; Step 2: Constructing a register direct loading mechanism based on explicitly defined local arrays; combining contiguous address layout, explicitly defining fixed-size local arrays in the kernel, and utilizing the compiler's register allocation mechanism to construct a direct data path from global memory to registers; Step 3: A register-level instruction static refactoring method based on orthogonal computation flow; employing an explicit code refactoring strategy to transform micro-tensor operations into hardware-optimal instruction sequences. This invention achieves end-to-end performance improvement from memory access to computation through a coherent optimization path of "linear address mapping—direct register loading—static instruction refactoring".

The application discloses a register allocation management method and device of a shader, equipment and a medium, and belongs to the technical field of computers. The method comprises the following steps: obtaining a fused computing shader fused by at least two kinds of shaders; based on the complexity of the fused computing shader and a preset graphics processor hardware threshold, setting a target thread bundle concurrency number; determining a register upper limit corresponding to each thread bundle according to the associated parameters of the graphics processor and the target thread bundle concurrency number; if the register usage of a single thread bundle of the fused computing shader exceeds the register upper limit, marking a virtual variable exceeding the register upper limit as an overflow candidate object; mapping the overflow candidate object to shared memory through a compiler; and executing the fused computing shader after compilation optimization. The technical scheme can make full use of the idle shared memory resources of a GPU, effectively improve the thread bundle concurrency degree of the GPU, and greatly reduce the access delay of overflow data.

The application relates to a register resource allocation method, computer equipment, a readable storage medium and a program product. The method comprises the following steps: constructing a function group through a calling relationship between functions, the function group comprising a coroutine kernel function and at least one coroutine sub-function; creating a resource record table corresponding to the function group, the resource record table being used for recording register resources allocated for the coroutine kernel function and / or the coroutine sub-function in the function group; and performing register allocation for the coroutine kernel function and the coroutine sub-function in the function group based on the resource record table. The method can meet the demand that local variable register resources are isolated and shared variable register resources are consistent in a cooperative mode, thereby improving parallel computing efficiency.

The invention relates to a vector register allocation method, electronic equipment and a medium, and the method comprises the following steps: S1, setting a default maximum executable thread count N0 in a compiler, and generating a default executable file; s2, generating the quantity P0 of vector registers which are defaulted and distributed for each thread; s3, starting a kernel function to obtain a thread count N1 input by a user, judging whether N1 is greater than N0 or not, if so, executing S4, otherwise, executing S5; s4, the compiler carries out recompilation based on the thread number N1 input by the user to generate an updated executable file, the number P1 of vector registers distributed for updating of each thread is generated, P1 vector registers are distributed for each thread, and the test case is executed based on the updated executable file; and S5, allocating P0 vector registers for each thread, and executing the test case based on the default executable file. According to the invention, the execution speed of the test case is improved.

The invention discloses a time-space isolated high-real-time control logic compilation optimization method and system. The method comprises the steps that a compiling system reads user logic and task information, a compiling space is divided according to POUs in the user logic, a task queue is constructed based on the task information, grammar and semantics of the POUs in the compiling space are analyzed, and SSA-based primary representation is generated; marking align attributes of structural member variables in user logic according to the size of a cache line of a target platform, marking array member variables in the user logic by using dynamic distribution, calculating access frequencies of all types of variables in a basic block, and determining variables to be replaced based on the access frequencies; and replacing the to-be-replaced variable with a temporary variable in the basic block, and performing memory layout and register subordination on all marked variables. According to the method, cache space-time isolation is realized through collaborative design of the spatial layout of the data structure and the register allocation strategy during compiling, the program execution efficiency is improved, and the cache miss overhead is reduced.

The embodiment of the invention provides a register allocation method, which is characterized in that when a weight is set for an edge in a target network, the weight is positively correlated with the distance between the edge and a key point, and the weight between nodes and the distance between a target position and the key point are simultaneously activated through explicit constraint of an energy function in iterative optimization. The target network can automatically arrange an overflow or reloading instruction at a code position closer to a key operation during iterative convergence, so that after the lifetime is segmented, the byreg interval is as short as possible, a physical register can be used by more variables, and the pressure of the physical register and the overflow instruction are reduced. In general, the register allocation method ensures that the finally determined target position not only can relieve physical register conflicts, but also can effectively reduce invalid register occupation time caused by the fact that an instruction insertion point is too far away from a key point, so that memory access overhead is reduced on the whole, and the utilization rate and execution performance of the register are improved.

In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

The application relates to the computer technical field, in particular to a register-allocated instruction scheduling method and device, a computer device and a storage medium. The method comprises the following steps: obtaining a machine instruction sequence to which a physical register has been allocated; determining scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; constructing a global instruction scheduling model according to the scheduling dependency information and the scheduling characteristic information; the global instruction scheduling model comprises scheduling constraint information determined according to the scheduling characteristic information; solving the global instruction scheduling model to obtain target transmission periods corresponding to the instructions, with the scheduling constraint information being a solving condition, the transmission clock period of each instruction being a solving variable, and the earliest clock period in which all the instructions are executed completely being a solving target; and allocating and scheduling the instructions in a register-allocated instruction scheduling stage based on the target transmission periods. The application provides an instruction scheduling method with better scheduling effect.

This invention provides a dynamic binary translation method for stack-based floating-point architectures using rule-based translation, expanding the applicability of translation rules and improving the support of existing dynamic binary translation systems for stack-based floating-point instruction sets. The specific operation of this invention is as follows: During the translation rule matching process, the correctness of the translation rules is ensured by virtualizing stack registers, thereby generating the correct target architecture instruction sequence in the instantiation of translation rules; when generating target code, the characteristics of the floating-point register stack are considered, and register allocation constraints are used to allocate registers on the floating-point stack. By identifying the target register and performing pop operations, the source architecture registers and target architecture registers are synchronized, ultimately generating an efficient target architecture floating-point instruction sequence. Compared to software-simulated floating-point instruction translation methods, the method of this invention achieves efficient dynamic binary translation while ensuring correct translation.

This application relates to the field of compilers, and in particular to a method for dynamically allocating caller-saved register storage space. Applied to the register allocation stage, it includes the following steps: obtaining the set of caller-saved registers that need to be saved at the current call point; obtaining the required storage space size N for the current call point based on the set of caller-saved registers; allocating a contiguous storage space of size N for this call by adjusting the stack pointer before generating the save instruction; writing the values ​​of the caller-saved registers that need to be saved at the current call point into the contiguous storage space of size N; executing the function call instruction; after the function call returns, restoring the values ​​of each caller-saved register written in the contiguous storage space of size N to the corresponding caller-saved register; and restoring the stack pointer to release the contiguous storage space of size N. This invention can solve the problems of stack space waste, high complexity, and susceptibility to errors.

The invention provides a physical register distribution method and device. The method comprises the steps that an instruction distribution unit determines the required number of physical registers according to a microinstruction; when the number of the tokens of the idle complete physical registers is larger than or equal to the required number, the corresponding tokens are reduced, and an instruction renaming unit is triggered to distribute the physical registers; when the number of the tokens is smaller than the required number, physical register distribution is not carried out; the instruction renaming unit sequentially selects complete or single physical registers meeting the required data size when the physical registers are distributed, and distributes the complete or single physical registers to the corresponding microinstructions; wherein a single physical register is preferentially selected; when a single physical register is selected, a corresponding number of tokens of idle complete physical registers are returned to the beat instruction distribution unit; renaming the register, and updating the mapping relation of the register; the number of complete or single physical registers can be dynamically adjusted through a dynamic adjustment mechanism.

Image processing pipelines are implemented as a series of stages, where each stage receives as its input output from a previous stage (or input to the entire pipeline). Inefficiencies can exist in such pipelines, related to the way in which the stages utilize resources. For example, a simple way of assigning memory or registers to such stages is to simply assign independent sets of memory or registers to each stage. This can be inefficient in the event that data is reused between stages. To alleviate these issues, an entity such as a compiler analyzes the operations to run at each stage and extracts commonly used resources to be reused between stages. In addition, stages of an image processing pipeline often use image data in different orders. To improve cache performance, the compiler or other entity transforms data received from previous stages to accommodate the access patterns of subsequent stages.