58 results about "Register assignment" patented technology

The embodiment of the invention provides a register overflow optimization method and device and a storage medium, and is applied to the technical field of chips. In the method, for each virtual register in a target program, based on a physical register type supported by an instruction operand where the virtual register is located, the virtual register is optimized; selecting a corresponding target register class from N candidate register classes, wherein N is greater than 1; allocating a first physical register in the target register class to the virtual register; when register overflow occurs, a target register is selected from the allocated first physical registers, the instruction operand stored in the target register overflows to the second physical registers in the other N-1 candidate register classes, and compared with the mode that the instruction operand overflows to the memory to generate read-write operation on the memory, the instruction operand stored in the target register overflows to the second physical registers in the other N-1 candidate register classes; according to the method, different types of physical registers are overflowed, read-write operation aiming at the physical registers is generated, the pressure of the registers is relieved, the performance overhead of the overflowed memories is reduced, and the register distribution efficiency is improved.

The invention relates to a register management method and device, electronic equipment and a storage medium. The method comprises the following steps: allocating a shared on-chip storage space for registers of a plurality of processing units in processing equipment; setting a write-in mark corresponding to the register of each processing unit in an array of the processing equipment; in response to execution of the first command, reading register data of the target register from the off-chip storage space, storing the register data in the on-chip storage space, and setting a write-in mark corresponding to the target register in the array to be valid; and in response to execution of the second command, determining an effective target write-in mark from the array, reading register data corresponding to the target write-in mark from the on-chip storage space, and writing the register data into a target register of the processing unit indicated by the target write-in mark. The embodiment of the invention can improve the operation efficiency of the processing equipment.

A method of rendering in a graphics processing system comprising compiling a program for a dual phase fragment task by a compiler, the first phase of the program being executed at a fragment rate and the second phase or the program being executed at a sample rate with the compiler being configured to determine data comprising the number of registers required per fragment in the first phase, the number of registers common between the first and second phase per fragment and the number of registers required per sample for the second phase to a processor. The compiled program and data are provided to a processor comprising the number of registers required per fragment in the first phase, the number of registers common between the first and second phase per fragment and the number of registers required per sample for the second phase. The processor obtains a fragment shading rate value and uses this together with least the number of registers required in the compiled program to compute the number of registers needed per fragment.

A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture / shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.

The invention discloses register allocation of multi-stage tasks. Within a graphics processing system, a plurality of different shading programs may be executed by a single processor on multiple threads. For each shading program, a plurality of registers are used to store data for the respective shading program. Accordingly, for a plurality of shading programs executing on a plurality of threads, a plurality of registers are allocated to each program or thread being executed. However, there is a limited number of registers available, so efficient allocation of the registers optimizes performance. Generally, an unnecessary number of registers is assigned to each shading program, but the present invention provides a method of assigning a correct number of registers based on the size of a segment being shaded.

Aspects presented herein relate to methods and devices for graphics processing units including an apparatus. The apparatus may load a set of values from a plurality of memories to a set of registers, where the plurality of memories includes at least one first memory and at least one second memory. Further, the apparatus may determine whether (1) a storage level for the at least one second memory is less than a maximum storage level, or (2) at least one first value in the set of values is selected for a register spill operation and will be utilized for an instruction that is after an instruction threshold. The apparatus may also store (1) the at least one first value in the at least one second memory or (2) at least one second value in the set of values in the at least one second memory.

A computer-implemented method for allocating registers for multi-core programs. The method includes generating core-specific programs for execution units of cores, wherein each program contains core-specific configurations. The method includes analyzing the core-specific programs to identify core-specific differences. The method includes creating a uniformized program that consolidates semantics of all programs for the execution units while retaining operations to account for core-specific differences. The method includes performing live range analysis of the uniformized program to identify active intervals for variables and creating segmented live ranges to partition the intervals into global and core-specific segments. The method includes allocating registers to the execution units using the segmented live ranges and multi-casting the uniformized program to the execution units of the cores.

The invention relates to a register resource allocation method, computer equipment, a readable storage medium and a program product. The method comprises the following steps: constructing a function group through a calling relationship between functions, wherein the function group comprises a coroutine kernel function and at least one coroutine subfunction; creating a resource record table corresponding to the function group, wherein the resource record table is used for recording register resources allocated to coroutine kernel functions and / or coroutine sub-functions in the function group; and carrying out register allocation on the coroutine kernel function and the coroutine sub-function in the function group based on the resource record table. By adopting the method, the requirements of local variable register resource isolation and shared variable register resource consistency in a collaborative mode can be met, so that the parallel computing efficiency is improved.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

An apparatus and method for eliminating load instruction execution. For example, one embodiment includes: circuitry to track execution of a plurality of load instructions and responsively update tracking tables; allocation circuitry to allocate a first source register to an instance of the first load instruction and to identify locations of the corresponding data elements in the cache line based on the tracking tables; execution circuitry to load data corresponding to the instance of the first load instruction from the cache line and to load the data elements corresponding to instances of the subsequent load instructions to the same source register; the allocation circuitry to indicate the first source register to the instances of the subsequent load instructions and respective locations of the data elements in the first source register, the instances of the subsequent load instructions to move the respective data elements from the first source register to destination registers.

A system and method for register coalescing is described. The system comprises a CORF, a coalescing-aware register file design for GPUs that simultaneously reduces the leakage and dynamic access power, while improving the overall performance of the GPU. CORF achieves these properties by enabling the reads to multiple operands that are packed together to be coalesced, reducing the number of reads to the RF, and improving dynamic energy and performance. CORF combines compiler-assisted register allocation with a reorganized register file (CORF++) in order to maximize operand coalescing opportunities.

The invention provides a random instruction sequence generation method, a random instruction sequence generator and a random instruction sequence verification system. N instances are created according to microinstruction quantity parameters in a target test case; determining an instruction slot identifier and a target instruction library corresponding to each instance according to the number of instruction slots; determining a matching instruction of the instance according to the target instruction library; performing register allocation according to the matching instruction of each instance, and determining information of each register in the microinstruction corresponding to the instance to obtain a corresponding assembly instruction; and generating an assembly instruction file according to the sorting number corresponding to each instance and all the assembly instructions, wherein the assembly instruction file comprises a random instruction sequence formed by the assembly instructions according to the sorting numbers corresponding to the instances and an instruction slot identifier corresponding to each assembly instruction. A random instruction sequence matched with the processor of the ultra-long instruction word framework can be generated, various test scenes can be simulated and completed, and the method is used for verifying the processor of the ultra-long instruction word framework.

The application discloses a DSP-oriented VLIW scheduling and packing method, which comprises the following steps: step 1, performing an LLVM IR optimization PASS sequence; step 2, constructing an instruction dependency graph (IDG); step 3, scheduling and packing before register allocation according to the global IDG; and step 4, reconstructing the IDG according to a register allocation result, and then scheduling and packing after the register allocation according to the reconstructed IDG. The application discloses a detailed IDG based on an SSA format, reveals potential parallelism between instructions, allows a compiler to identify opportunities for parallel execution at an earlier stage, avoids the parallelism loss problem introduced by the traditional method in the post-register allocation packing, and significantly improves the execution efficiency of a program on a DSP platform.

The invention relates to register allocation. The shader program can include a condition portion that executes only in response to a particular condition being satisfied. The use of the condition portion may require different numbers of registers. Thus, this use of the condition portion potentially causes overallocation of registers. Accordingly, there is provided a method of rendering in a graphics processing system using a shader program having a condition segment applied only in response to satisfaction of a condition, the method comprising: compiling, by a compiler, the program, the compiling comprising identifying the condition segment; reading, by the resource allocator, constants that determine a result of the condition; determining, by the resource allocator, whether the condition is satisfied; and allocating, by the resource allocator, a number of registers.

The invention provides a register allocation method and device, an instruction transmitting method and device and electronic equipment, and relates to the technical field of computer processors, the method comprises the steps that N allocated register groups are acquired, and each register group comprises at least one physical register; selecting a target physical register group from the N register groups according to a register distribution rule when responding to the existence of the target logic register for register distribution; and allocating the target physical register group to the target logical register. By selecting the corresponding physical register group according to the operation type of the target instruction, resource isolation and special path allocation of different function instructions are realized, register resource competition is effectively avoided, a data path is optimized, access delay and power consumption are reduced, and the parallel execution efficiency, the function module utilization rate and the overall performance of a processor are improved.

The invention relates to the field of compiler optimization, and provides a register allocation method, which comprises the following steps of: firstly, reversely scanning a control flow diagram, and constructing an active range table for all variables so as to accurately record a dead interval of each variable; secondly, carrying out dead interval matching and multiplexing operation in a register allocation process; and finally, carrying out weight calculation by combining variable active range and dead interval features, and optimizing an overflow decision. The invention aims to realize register multiplexing by identifying and utilizing the dead interval in the variable active range, thereby improving the utilization rate of the register, reducing the overflow of the register and improving the execution performance of the program.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.

An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data valu

Embodiments of the present application provide a register overflow optimization method and device and a storage medium, applied to the chip technical field, in the method, for each virtual register in a target program, based on the physical register type supported by the instruction operand where the virtual register is located, a corresponding target register class is selected from N candidate register classes, N is greater than 1; a first physical register in the target register class is allocated to the virtual register; when a register overflow occurs, a target register is selected from the allocated multiple first physical registers, and the instruction operand saved in the target register is overflowed to a second physical register in the other N-1 candidate register classes. Compared with overflowing the instruction operand to the memory to generate read and write operations on the memory, the present application overflows to different types of physical registers, generates read and write operations on the physical registers, relieves the pressure of the registers, reduces the performance overhead of overflowing to the memory, and improves the register allocation efficiency.

The application relates to the field of register allocation of a compiler, in particular to a register selection method based on a bit vector and a configurable mapping. The method comprises the following steps: obtaining a category mask corresponding to a target constraint and an availability bit vector; each bit in the availability bit vector corresponds to a register; if 0 in the availability bit vector represents an idle corresponding register and 1 represents an occupied corresponding register, then performing a NOT operation on the availability bit vector, performing a bitwise AND operation on the vector obtained after the NOT operation and the category mask corresponding to the target constraint, and obtaining a vector obtained after the bitwise AND operation; and performing a first position bit detection on the vector obtained after the bitwise AND operation, and determining a register corresponding to a first value 1 bit number obtained after the detection as a selected idle register satisfying the target constraint. The application can improve register category filtering efficiency and reduce the determination cost of register availability.

This application relates to the field of compilers, and in particular to a method for dynamically allocating caller-saved register storage space. Applied to the register allocation stage, it includes the following steps: obtaining the set of caller-saved registers that need to be saved at the current call point; obtaining the required storage space size N for the current call point based on the set of caller-saved registers; allocating a contiguous storage space of size N for this call by adjusting the stack pointer before generating the save instruction; writing the values ​​of the caller-saved registers that need to be saved at the current call point into the contiguous storage space of size N; executing the function call instruction; after the function call returns, restoring the values ​​of each caller-saved register written in the contiguous storage space of size N to the corresponding caller-saved register; and restoring the stack pointer to release the contiguous storage space of size N. This invention can solve the problems of stack space waste, high complexity, and susceptibility to errors.

Reducing the range of activity of variables of register allocation for a structured control flow program is provided. The method includes defining an affine expression for each static single assignment SSA variable contained in an input program of a computer compiler. The affine expression of the SSA variable in the input program is derived by replacing the affine expression of the input operand involved in the calculation of the SSA variable. The method defines dependency edges between nodes representing SSA variables in the dependency graph, where sources and destinations of the dependency edges represent definitions and uses of the SSA variables. The method identifies, among the dependent edges, one or more overlapping dependent edges having the same source, and eliminates longer ones of the overlapping dependent edges according to the derived affine expression.

The invention provides a dynamic register allocation method and system based on an RISC-V architecture, and belongs to the technical field of computers. The method comprises the steps that task characteristic data are received in real time; predicting a register demand corresponding to the task based on the task characteristic data; determining a partition decision of a self physical register based on the register demand; and dividing the register based on the partition decision, controlling the partition control register to dynamically configure the physical address range and the access authority of each physical register partition, and controlling the physical memory protection unit to configure the access rule of each physical register partition. According to the invention, the register demand is predicted based on the task characteristic data, the register is partitioned based on the register demand, and the dynamic allocation of the register is realized by expanding the type of the control and state register and the function of the physical memory protection unit, so that the allocation of the register adapts to the dynamic change of the task load during operation; and resource waste or conflict is avoided.

The present application relates to a micro-matrix operation instruction level parallel optimization method based on a heterogeneous many-core processor system, and belongs to the technical field of electronic information, and comprises the following steps: step 1: a linear address mapping architecture based on particle priority; a multi-dimensional tensor space in a physical problem is mapped to a one-dimensional linear physical address space of a GPU; step 2: a register direct loading mechanism based on explicit definition of a local array is constructed; in combination with a continuous address layout, a fixed-size local array is explicitly defined in a kernel, and a direct data path from a global memory to a register is constructed by using a register allocation mechanism of a compiler; and step 3: a register level instruction static reconstruction method based on an orthogonal calculation flow; an explicit code reconstruction strategy is adopted to convert micro-tensor operation into an instruction sequence optimal for hardware. Through a coherent optimization path of "linear address mapping-direct register loading-instruction static reconstruction", the present application realizes full-link performance improvement from memory access to calculation.

The application discloses a register allocation method, device, equipment, medium and product, and the method comprises the steps of obtaining an operation instruction to be allocated, determining an operation width identifier of the operation instruction to be allocated; determining a register allocation mode of the operation instruction to be allocated according to the operation width identifier and a register sharing condition, wherein the register allocation mode comprises a shared register allocation mode and a separate allocation mode; performing physical register allocation on the operation instruction to be allocated based on the register allocation mode, and generating an enhanced renaming table, and each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register. By splitting a single 64-bit physical register into two independent 32-bit sub-registers and realizing shared use, the shared or separate allocation mode is dynamically selected based on the instruction width, space waste caused by using only 32 bits but occupying a complete 64-bit register can be avoided, dynamic power consumption is reduced, and the register utilization rate is significantly improved.

The invention discloses a register allocation method and device, a computer program product and a readable storage medium, belongs to the field of program compiling, is used for allocating registers for variables during program compiling, and solves the problem that registers cannot be allocated to a large number of variables in a program. Considering that if a node of which the degree is greater than the total number of registers exists in the conflict graph, part of neighbor nodes of the node need to be overflowed to a memory; the neighborhood node area (the node and the adjacent nodes thereof) of one node has divisibility; the method comprises the following steps: determining a target node of which the degree is greater than the total number of registers in a conflict graph, dividing a neighborhood node region of the target node into a plurality of node sub-regions, and meeting the following conditions: each node sub-region comprises the target node, and the degree of the target node in the node sub-region is less than the total number of registers; therefore, the situation that part of neighbor nodes of the target node cannot be allocated to the register and are overflowed to the memory is avoided, and the running efficiency of the executable program obtained through final compiling can be improved.

The application provides a random instruction sequence generation method, a generator and a verification system. N instances are created according to a microinstruction quantity parameter in a target test case. Instruction slot identifiers and a target instruction library corresponding to each instance are determined according to an instruction slot quantity. Matching instructions of the instances are determined according to the target instruction library. Register allocation is performed according to the matching instructions of each instance, each register information in the microinstruction corresponding to the instance is determined, and corresponding assembly instructions are obtained. An assembly instruction file is generated according to the sorting number corresponding to each instance and all the assembly instructions. The assembly instruction file comprises a random instruction sequence composed of the assembly instructions according to the sorting number corresponding to the instance and the instruction slot identifier corresponding to each assembly instruction. The random instruction sequence matched with a very long instruction word architecture processor can be generated, various test scenes can be simulated, and the verification of the very long instruction word architecture processor can be completed.

The application discloses a processor supporting register release, a register release method, a display card and equipment, and belongs to the technical field of register management. The processor comprises a plurality of registers, an allocation management unit and a resource management unit. The allocation management unit is used for allocating at least two register sets for a first thread group, and each register set in the at least two register sets comprises at least one register in the plurality of registers. The resource management unit is used for releasing a first register set in response to the end of use of all registers in the first register set by the first thread group, and the first register set is one register set in the at least two register sets. The processor supports early release of the first register set when the first thread group ends the use of all registers in the first register set, thereby avoiding the problem of low utilization of register resources caused by long-term occupation of the first register set by the first thread group.

Reducing live range of variables for register allocation of structured control-flow programs is provided. The method comprises defining an affine expression for each static single assignment (SSA) variable contained in an input program for a computer compiler. The affine expression of a SSA variable in the input program is derived by substitution of affine expressions of input operands involved in computation of the SSA variable. The method defines dependence edges between nodes representing the SSA variables in a dependence graph, wherein source and destination of dependence edges represent definition and use of the SSA variables. The method identifies one or more overlapping dependence edges with a same source among the dependence edges and eliminates the longer of the overlapping dependence edges according to the derived affine expressions.

The present disclosure relates to the technical field of processors. Provided are a processor structure based on odd-even scheduling and allocation, and a chip and an electronic device. In the processor structure based on odd-even scheduling and allocation provided in the present disclosure, a free physical register file is divided into an odd part and an even part in a renaming phase, and whether an odd physical register or an even physical register is allocated for the current renaming operation is determined according to an instruction type. The embodiments provided by the present disclosure can reduce by half the number of write ports of a register file, and can effectively perform the allocation and instruction scheduling of physical registers in combination with a register allocation balancing algorithm.