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Compiler system based on TCore configurable processor

A processor and compiler technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as difficult to use compilation technology, complex constraints, etc., and achieve the effect of solving the inefficiency of compilers

Inactive Publication Date: 2010-04-14
TIANJIN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the complexity of the established constraint relationship, it is often difficult to be used in the actual compilation technology
Experiments show that this method is only suitable for small-scale code optimization within basic blocks

Method used

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  • Compiler system based on TCore configurable processor
  • Compiler system based on TCore configurable processor
  • Compiler system based on TCore configurable processor

Examples

Experimental program
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Embodiment Construction

[0044] The present invention saves and organizes a large amount of program analysis information in an intermediate format at the front end of the compiler of the Tcore microprocessor, performs more complex code analysis and code conversion, and uses XML language to organize rich architecture information to complete the retargetable design of the compiler back end. The Tcore compiler architecture based on this idea is as follows figure 1 shown. This architecture adopts the SUIF2 and MACHSUIF developed by Stanford University to construct the front end of the compiler. SUIF2101 is responsible for converting the high-level language description of the application into the first-level intermediate machine language (expressed as SUIF IR) 102, and outputting it to the extensible compilation framework ( MACHSUIF) 103 for subsequent processing. Extensible Compilation Framework (MACHSUIF) is an extensible compilation framework that is convenient for constructing the backend of a compile...

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Abstract

The invention discloses a compiler system based on a configurable processor, adopting an intermediate language format to carry out the organization of a compiler and finishing the distribution and instruction scheduling of a register by a linear trace and a genetic algorithm, wherein the compiler comprises an SUIF2, a first-level intermediate machine language SUIF IR, an extensible compiling framework MACHSUIF, a second-level intermediate machine language SUIFVM, a consolidated extension interface Machine Library Interface, a serial configurable processor code Sequential Code, an architecture parser, a code generator, a configurable architecture description file ADT and a parallel configurable processor code. The invention enables the compiler to efficiently finish the generation of codes and solves the long-term problem that the compiler based on a TTA architecture processor has low efficiency through the combination of the front end of the compiler based on an intermediate formate and the rear end of the compiler based on two heuristic algorithms of the linear trace and the genetic algorithm.

Description

technical field [0001] The invention relates to a configurable microprocessor in an embedded system in the field of computer technology, in particular to the development technology of a compiler in a configurable microprocessor. Background technique [0002] Currently, embedded systems are widely used in many fields. The embedded microprocessor determines the performance of the embedded system to a large extent. Mainstream microprocessors such as ARM, MIPS, PowerPC, etc. are designed for general purposes, with powerful functions and support for various operations and data types. This general design limits the possibility of developing parallelism in a specific field. [0003] The configurable microprocessor overcomes the above disadvantages. It customizes the instruction set and processor architecture for specific tasks, which not only maintains the flexibility of the processor, but also makes the performance close to that of an application-specific integrated circuit (ASI...

Claims

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Application Information

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IPC IPC(8): G06F9/45G06N3/12
Inventor 魏继增郭炜史再峰王正华刘壮丽
Owner TIANJIN UNIV
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