197 results about "Data flow diagram" patented technology

A system and method for intelligently generating computer code. The system being comprised of a local computer, which is connected to a remote computer via a network system or the Internet and which is capable of exchanging files with the remote computer. The local computer is further comprised of a document manager for transferring files between the local computer and the remote computer and for providing enhanced file management functions. The document manager works in connection with the server module, the site manager and the connectivity layer to connect to remote computers, to transparently exchange files with the remote computer and to manage server profiles and connection information that is related to remote computers and transferred files. Once the file is transferred to the local computer, the editor can modify the code associated with the file; the editor is also capable of creating new files. The visualizer is capable of displaying a program flow diagram and a data flow diagram, which are comprised of program flow icons and data flow arrows to depict the code in terms of processing blocks and data blocks. To assist in developing new code or editing existing code, the template manager allows the user to browse through a directory of existing code sections or templates and to copy templates into the selected code for editing. For allowing the editor to process code that is written in different Data Management System programming languages and for creating the program flow icons, the parser layer detects the file type of a selected file and activates the rules and logic that apply to the corresponding Data Management System.

A system and method for implementing a debugging graphical program in a main graphical program. A user can associate a debugging graphical program with a wire in a data flow diagram in order to debug and / or analyze the main graphical program. This association does not change or require recompilation of the main graphical program. The debugging graphical program, or smart probe, receives the data from the main graphical program, analyzes this data, and can perform one of several actions. The debugging graphical program can display the data in the wire, generate statistics based on received data, log statistics or data to a file, or perform other analysis functions. The debugging graphical program can also cause the main graphical program into halting execution, entering single stepping mode, etc. The user may choose a debugging graphical program already present, or create one using graphical programming techniques.

System and method for optimizing a data flow diagram based on access pattern information are described. Access pattern information for a data flow diagram may be received. The data flow diagram may include a plurality of interconnected actors, e.g., functional blocks, visually indicating functionality of the data flow diagram. The access pattern information may include one or more of: input pattern information specifying cycles on which tokens are consumed by at least one of the actors, or output pattern information specifying cycles on which tokens are produced by at least one of the actors. A program that implements the functionality of the data flow diagram may be generated based at least in part on the access pattern information.

Developing an ETL system for transforming data prior to loading the data into a data warehouse. An embodiment of the invention automatically generates configuration files from an input data flow diagram defining the ETL system. The configuration files or other metafiles control execution of the processes illustrated in the data flow diagram. The invention includes a notation for use in the data flow diagram.

Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool allows the programmer to define a region divided into multiple blocks, wherein each block is associated with data operated on by code segments of the data flow program. The development tool also maintains dependencies among the blocks, each dependency indicating a relationship between two blocks that indicates that the portion of the program associated with a first block of the relationship needs the resultant data provided by the portions of the program associated with a second block of the relationship. The development tool supports several debugging commands, including insertion of multiple types of breakpoints, adding and deleting dependencies, single stepping data flow program execution, and the like.

The embodiment of the invention discloses an information processing method and device. The method comprises the steps that the basic elements of SQL codes are recognized based on a first strategy; the basic elements analyzed from the SQL codes are subjected to combination operation, SQL sentences are obtained, and a syntax tree is established; the SQL sentences in the syntax tree are subjected to traversal, based on the types of the basic elements in the SQL sentences obtained after traversal and the corresponding relationship of the types of the basic elements and nodes, nodes are correspondingly established for the basic elements in the SQL sentences obtained after traversal, and the intermediary language description of the syntax tree is obtained; and based on the intermediary language description of the syntax tree, a data flow diagram corresponding to the SQL codes is established. According to the technical scheme of the embodiment, the corresponding data flow diagram can be obtained quickly and accurately based on the SQL codes, developing personnel can carry out secondary development or upgrading on a system conveniently based on the data flow diagram, and implementation cost is lowered.

This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functionality and characteristics of a block type, and each block type has associated templates. These templates provide maps for the creation of test values that verify the functionality of particular instances of that block type. Signal propagation allows the generation of diagram-level test cases that verify particular characteristics of a single embedded block. The methods disclosed for signal propagation utilize range intersection, equivalence classes, and block type formulae to create efficient and complete test cases. This test generation method would preferably be repeated until all blocks in a data flow block diagram were verified in their respective contexts, and it creates test cases that cover multiple time steps.

An electronic device and method are provided to enable a user to control characteristics of graphical objects of a graphical model environment without requiring manual entry of characteristics into each object. Propagation of characteristics from one or more objects to one or more objects may be specified and performed without requiring manual entry of characteristics into each objects. Examples of graphical model environments can include block diagrams, data-flow diagrams, state-based diagrams, circuit diagrams, mechanical diagrams, biological diagrams, network diagrams and software diagrams.

A system is provided for modeling and analysis of cybersecurity threats may include a data flow diagram (DFD) creator, threat indicator and threat analyzer. The DFD creator may identify elements of an information system, and compose a DFD including nodes and edges representing components and data flows of the information system. The threat indicator may identify a cybersecurity threat to a particular element of the information system, and add a secondary node representing the cybersecurity threat to the DFD to thereby produce a threat-model DFD for the information system. In metadata associated with the nodes, edges and secondary node, the DFD creator and threat indicator may provide structured information including attributes of the components, data flows and cybersecurity threat. And the threat analyzer may perform an analysis of the cybersecurity threat based on the threat-model DFD and metadata associated with the nodes, edges and secondary node thereof.

System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.

System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.

A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

The present invention discloses a power-aware compiling method, wherein the power model of an application program are established via building and analyzing the control flow chart and the data flow chart of the application program; each functional unit of the application program is assigned a power mode; a judgment is undertaken to determine whether the idle functional units are independent; if none dependency exists between those idle function units, the program codes of the same idle function units are merged into a new basic block, and the idle functional units are turned off for saving power; each new basic block is assigned an appropriate power mode; the basic blocks with the same power modes are merged to reduce the transitions between different power modes; thus, the power consumed by changing voltage or frequency can be decreased.

The present invention provides an instruction scheduling optimization method for a coarse-grained reconfigurable architecture compiler, comprising: configuring a multi-layer heterogeneous coarse-grained reconfigurable processor architecture that follows global synchronization; The data flow graph of the instruction is correspondingly optimized for the multi-layer heterogeneous coarse-grained reconfigurable processor architecture.

A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.

The invention relates to a data flow modeling and processing system to interact with a data processing tool. The data flow modeling and processing system comprises: a graphics user interface for creating a data flow diagram; an interfacial server connected to the graphics user interface for receiving the data flow diagram of the graphics user interface and analyzing into a command function; an executive end comprising the data processing tool, wherein the executive end is connected with the interfacial interface to receive the command function sent by the interfacial server for the purpose ofoperating and to transmit final results to the graphics user interface through the interfacial server. The data flow modeling and processing system has the advantages that the graphics user interfaceand the interfacial server allow a user to design and execute a data flow diagram through simple graphic design, processing efficiency is improved, designing and execution difficulty is relieved, thesystem is more widely applicable, visual operations can be performed, execution results can be fed back, a problem with execution of the data processing tool can be discovered and solved in time, andit is avoided that the prior art takes massive checking to locate the problem.

The invention relates to a visualization method for explaining a convolution neural network, and the method comprises the steps: preparing a convolution neural network model M and a training set S therefor; extracting all determination conditions of the model M in a decision making process; deciding the meanings of nerve cells through the nerve cells and the meanings of a human corpus, and generating intelligible meanings for all determination conditions; forming a decision making tree T, and taking a decision-making process as the decision-making process of the model M; converting the decision making tree T into a tree flow diagram; making a nerve cell meaning view; making a nerve cell relational graph; making a decision-making data flow diagram; and constructing an interactive visualization system.

The invention relates to an IFC data interaction-based engineering information delivery and sharing integrated management system. The information delivery and sharing method comprises the steps of firstly drawing a builder data flow chart; compiling an information delivery demand definition form; establishing information delivery IDM standards; by adopting a programming means and selecting BIM software Revit developed based on a .NET platform, performing programming of secondary development of the Revit by utilizing programming software Visual Studio 2015 through use of a C# programming language; establishing an interface for the Revit; inserting the standards into the interface; creating a self-defined panel; inserting three buttons into the Revit to realize the following three functions of (1) displaying demand definitions according to selected component elements, (2) searching for the demand definitions in a classified manner and (3) viewing the demand definition form; and performing secondary development on the Revit, thereby finishing the whole information delivery process. The information integrated management system comprises an information delivery platform structure which can be divided into a data source, a structure layer, a data layer, a model layer, a delivery layer, a platform layer and an interface layer module. The information standardized delivery of a BIM is realized by utilizing IFC information standards.

The present invention extends to methods, systems, and computer program products for accessing and manipulating data in a data flow graph. A data flow graph includes one more transforms for transforming data from one or more data stores into different formats accessible to clients. Transforms can be configured to join and split data from the same or different data stores. A metadata tree logically represents the data flow graph including locations that provide output from transforms of the data flow graph. The locations can be referenced by clients to access transformed outputs. Clients can register dependencies on data at various locations and can request evaluation of the data in response to data changes at a corresponding data store. Clients can also request data changes be propagated back through the data flow graph to one or more data stores and implemented at the one or more data stores.

The invention provides a register allocation method for optimizing stack space, which comprises the following steps: 1, analyzing a program intermediate file by a register allotter to obtain a data flow diagram; 2, constructing interference patterns of program variables according to the data flow diagram; 3, optimizing the interference patterns to eliminate false interference edges; 4, trying to color the interference patterns, if the step is successful, indicating no variable overflow and stopping allocating the registers, and otherwise performing the next step; 5, abridging the interferencepatterns, and overflowing the low-priority variables to a stack; 6, allocating the number of actual physical registers for the highest-priority virtual registers; and 7, aiming at the overflow nodes of the step 5), inserting the corresponding codes, and querying the accurate interference patterns of the step 3) to allocate the same stack offset for noninterference overflow variables. The method for eliminating the false interference edges comprises the steps: for two interference variables, further analyzing interference variables which are not intersected with an inference register to deletea connection line of the two variables and eliminate the false interference edges.

System and method for implicit downcasting at compile time in a data flow program. A first data flow function in an object-oriented dataflow program is identified, where the first function includes an input of a parent data type and an output of the parent data type. The first function is analyzed to determine if the output preserves the run-time data type of the input. A second dataflow function in the object-oriented data flow program is identified, where the second function includes a program element that calls the first function, passing an input parameter of a child data type of the parent data type as input. If the analysis determines that an output parameter returned by the output of the first function will always be of the child data type, the program element is automatically configured at compile time to always downcast the output parameter from the parent data type to the child data type at run-time.

The invention discloses a control method and a control device of a cache resource of a shared cache type Ethernet switch, and relates to the communication field. The method includes following steps: receiving a data package and simultaneously performing hash calculation, then obtaining a flow index of the data package, and retrieving a data flow array according to the flow index to obtain flow information; retrieving a queue array according to a queue index to obtain the length of a current queue and a flow number of the queue; updating a used cache variable value of the flow information according to the length of the data package; carrying out different judging treatments of different flow behaviors according to a comparative result of an occupied cache value and a current credit value of the flow information with an average cache value, an attack flow credit threshold value, an attack flow cache value of a system; and updating the used cache value, the current credit value, an active flow count of the queue, the length of the queue in the flow information after forwarding the data package. The control method and the control device of the cache resource of the shared cache type Ethernet switch can respond timely according to a current use condition of the cache, discover an attack behavior rapidly, prevent the attack behavior from consuming the cache resources, and control network congestion effectively.

System and method for generating a data flow diagram. A first case structure may be specified. Each case of the first case structure that includes a respective plurality of input bound data flow nodes may be partitioned into one or more data flow diagram portions. The first case structure may be replaced with a first conditional structure and one or more second conditional structures. The first conditional structure may be operable to select one or more of the plurality of input bound data flow diagram portions in accordance with the conditions of the first case structure. The one or more second conditional structures may be operable to select at least one output from the plurality of input bound data flow diagram portions in accordance with the conditions of the first case structure. The partitioning and replacing may be performed automatically in response to specification of the first case.

System and method for generating a data flow diagram. A data flow diagram is provided that includes one or more non-input bound data flow (NIBDF) nodes, each with a respective functionality, and at least one of which is a subsystem node representing a non-input bound data flow sub-diagram comprising a plurality of interconnected nodes. All non-input bound data flow nodes in the data flow diagram are converted into input bound data flow (IBDF) nodes to produce an IBDF diagram, including: for each NIBDF subsystem node in the data flow diagram: partitioning the NIBDF sub-diagram into a plurality of IBDF sub-diagrams that operate according to input bound data flow semantics without changing data dependencies of the NIBDF sub-diagram, and including a plurality of IBDF nodes respectively representing the plurality of IBDF sub-diagrams in the IBDF diagram in lieu of the NIBDF subsystem node. The IBDF diagram is then stored.