Instruction scheduling optimization method for coarse-grained reconfigurable architecture complier

Abstract

The present invention provides an instruction scheduling optimization method for a coarse-grained reconfigurable architecture compiler, comprising: configuring a multi-layer heterogeneous coarse-grained reconfigurable processor architecture that follows global synchronization; The data flow graph of the instruction is correspondingly optimized for the multi-layer heterogeneous coarse-grained reconfigurable processor architecture.

Description

technical field [0001] The present invention relates to the field of reconfigurable computing, and relates to the parallel computing of reconfigurable processors and the compilation process of reconfigurable processors; more specifically, the present invention relates to an instruction for a coarse-grained reconfigurable architecture compiler Scheduling optimization method. Background technique [0002] Reconfigurable processor is an important product to meet people's demand for computing speed and computing versatility in the information age. It has both the advantages of general-purpose processors and application-specific integrated circuits (ASICs). A typical coarse-grained reconfigurable processor is composed of a main controller, a main memory DDR (Double Data Rate) and a reconfigurable processing unit (Reconfigurable Processing Units, RPU). The data transmission between each part is realized through the bus. The main controller is used to run the operating system and ...

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Problems solved by technology

It can be seen from these studies that most scheduling algorithms lack systematic analysis and optimization of data flow graphs before mapping them to reconfigurable arrays, and the structure of data flow graphs is not completely suitable for reconfigurable array structures. The configuration affects the computing performance. At the same time, these algorithms have high time complexity and long compilation time.

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