Instruction scheduling optimization method for coarse-grained reconfigurable architecture complier

An instruction scheduling and optimization method technology, applied in the instruction scheduling optimization of the coarse-grained reconfigurable architecture compiler, the compilation process of the reconfigurable processor, and the parallel computing field, which can solve the problems affecting the computing performance, long compilation time, lack of data Analysis and optimization of flow graph systems

Inactive Publication Date: 2016-08-17
SHANGHAI JIAO TONG UNIV
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  • Description
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Problems solved by technology

It can be seen from these studies that most scheduling algorithms lack systematic analysis and optimization of data flow graphs before mapping them to reconfigurable arrays, and the structure of data flow gra

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  • Instruction scheduling optimization method for coarse-grained reconfigurable architecture complier
  • Instruction scheduling optimization method for coarse-grained reconfigurable architecture complier
  • Instruction scheduling optimization method for coarse-grained reconfigurable architecture complier

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Embodiment Construction

[0028] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0029] Based on the analysis of the present situation, the present invention proposes a brand-new instruction scheduling optimization method for a coarse-grained reconfigurable compiler, which is specifically developed from the following two aspects.

[0030] 1. Configure a multi-layer heterogeneous coarse-grained reconfigurable processor architecture that follows global synchronization

[0031] The present invention adopts a coarse-grained reconfigurable processor with a new architecture, which includes a three-layer heterogeneous structure such as figure 1 shown.

[0032] First, the multi-layer heterogeneous coarse-grained reconfigurable processor architecture includes: a single main controller 100 (for example, the main controller is impleme...

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Abstract

The present invention provides an instruction scheduling optimization method for a coarse-grained reconfigurable architecture compiler, comprising: configuring a multi-layer heterogeneous coarse-grained reconfigurable processor architecture that follows global synchronization; The data flow graph of the instruction is correspondingly optimized for the multi-layer heterogeneous coarse-grained reconfigurable processor architecture.

Description

technical field [0001] The present invention relates to the field of reconfigurable computing, and relates to the parallel computing of reconfigurable processors and the compilation process of reconfigurable processors; more specifically, the present invention relates to an instruction for a coarse-grained reconfigurable architecture compiler Scheduling optimization method. Background technique [0002] Reconfigurable processor is an important product to meet people's demand for computing speed and computing versatility in the information age. It has both the advantages of general-purpose processors and application-specific integrated circuits (ASICs). A typical coarse-grained reconfigurable processor is composed of a main controller, a main memory DDR (Double Data Rate) and a reconfigurable processing unit (Reconfigurable Processing Units, RPU). The data transmission between each part is realized through the bus. The main controller is used to run the operating system and ...

Claims

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F8/45
Inventor 赵仲元刘毅超绳伟光何卫锋
Owner SHANGHAI JIAO TONG UNIV
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