26 results about "Interrupt priority level" patented technology

The invention relates to the technical field of system-on-chip service interrupt processing, in particular to a hardware Sequence-based SoC interrupt processing method, which comprises the following steps of: pre-programming an interrupt processing instruction sequence into an instruction random access memory (RAM), and configuring an instruction set, a sequence processor and an interrupt priority strategy of a task scheduler Sequence; receiving the interrupt signal by a task scheduler, and selecting a corresponding sequence processor according to an interrupt type; for the interrupt with low priority, the Sequencer directly executes the pre-stored instruction sequence to complete the interrupt response; and for high-priority interruption, the Sequencer caches the state of the register and sends a message packet to notify the CPU to perform cooperative processing. According to the method, interrupt autonomous response is achieved through hardware Sequence, zero CPU intervention is achieved in low-priority interrupt, a lightweight message mechanism is adopted in high-priority interrupt, and bandwidth occupation and power consumption are reduced while efficiency is improved.

The invention discloses a low-delay interrupt processing method and system of an intelligent control center, and belongs to the field of industrial control computer system architecture. The method comprises the following steps: analyzing an interrupt request to obtain an event type identifier; based on a predefined event priority mapping table, matching the event priority into a corresponding interrupt priority; selecting a path from a pre-allocated and physically isolated hardware response path set according to the interrupt priority; distributing the interrupt request and the context data to a pre-bound processing core through the selected path; and the processing core executes the preloaded simplified processing routine to generate a driving instruction. Through combination of event semantic mapping and physical isolation hardware paths, a deterministic low-delay response channel is provided for core emergency interrupt, system reliability is improved through a load balancing mechanism based on cache consistency, the problem of large delay jitter of high-concurrency interrupt processing of an industrial intelligent control center is effectively solved, and the system reliability is improved. And the real-time performance of the control system is obviously improved.

According to the energy storage system control method based on the interrupt task and the energy storage system provided by the embodiment of the invention, the unspecified interrupt vector of the processor in the energy storage system is configured as the target interrupt vector, and the interrupt priority of the target interrupt vector is set as the highest priority of the system; when it is detected that a preset emergency occurs in any energy storage device in the energy storage system, a target interrupt vector is triggered, so that a processor skips to execute a target interrupt service program pointed by the target interrupt vector; wherein the target interrupt service program is used for processing an emergency event of the energy storage equipment, and the target interrupt service program cannot be preempted by other interrupt programs in the execution process. According to the method, the non-specified interrupt vector of the processor is configured as the target interrupt vector with the highest priority, so that the emergency event can be quickly processed under the condition of not influencing other processes, and the service program is not preempted by other interrupts due to the characteristic of the highest priority, thereby ensuring that the emergency task is efficiently completed without delay.

An apparatus has an interrupt detection circuit to detect a first interrupt to be handled by a processing circuit in a target execution environment. The apparatus also has exception signaling circuitry to signal an exception to the processing circuitry in response to the accepted interruption. When the first interrupt satisfies at least one criterion, including when the target execution environment is not an active execution environment of the processing circuitry, the exception signaling circuitry is configured to signal a first exception or a second exception according to an interrupt priority associated with the first interrupt. When the interrupt priority exceeds a threshold priority, the first anomaly is signaled to preemptively trigger a given action wherein switching from the active execution environment to the target execution environment depends on the given action, and when the interrupt priority does not exceed the threshold priority, the second anomaly is signaled to preemptively trigger the given action wherein switching from the active execution environment to the target execution environment depends on the given action. The given action is not preemptively triggered.

The invention provides an interrupt control circuit and method, a chip and electronic equipment. When an interrupt event occurs at the same time, the plurality of sub-modules generate interrupt requests corresponding to respective interrupt events, and send the interrupt requests and interrupt priorities to the arbiter. And the arbiter obtains an arbitration result according to the plurality of interrupt priorities and the plurality of interrupt requests, and sends the arbitration result to the interrupt processor. And the interrupt processor determines target in-band interrupt data according to the arbitration result, and sends the target in-band interrupt data and the initiating signal to the I3C slave controller, so that the I3C slave controller sends the target in-band interrupt data to the I3C host. And after the sending is finished, the plurality of sub-modules send other interrupt requests except the interrupt request with the highest priority in the plurality of interrupt requests or the interrupt request of the target in-band interrupt data which is not successfully sent to the arbiter again so as to apply for arbitration again. Therefore, the interruption event which is not successfully sent and the interruption event which fails in arbitration can be prevented from being lost.

The invention relates to an MCU automatic test method and system based on interrupt priority triggering, efficient automatic test is realized through cooperative work of an automatic trigger interrupt module, a downloader, an MCU system configuration module, an interrupt priority configuration module, a comparative analysis module and a to-be-tested MCU, and an automatic configuration system is specifically designed to analyze an ATE test board instruction. The target program is called from the application program library and downloaded to the MCU test daughter board, and the full-parameter test can be covered without repeated burning. The MCU automatic test method comprises the following steps: dynamically modifying MCU configuration, writing multiple test configurations at one time, interrupting priority presetting to avoid function conflicts, and temporarily storing a test program through an SRAM (Static Random Access Memory) to avoid erasing original data. The problems that manual operation is tedious and time sequence debugging is difficult in a traditional ATE test are solved, and the method is suitable for semiconductor mass production and research and development verification scenes.

This invention discloses a safety monitoring method, electronic device, and storage medium for a vehicle instrument system. The method includes the following steps: periodically monitoring registers and notifying the interrupt system of any abnormal registers for appropriate handling; periodically checking whether the interrupt frequency recorded in a RAM area is normal; checking the priority of the interrupt system to determine if an interrupt priority error has occurred and taking corresponding fault response strategies; and checking whether unused interrupt numbers are being called in the interrupt service routine to determine if any null interrupts are being triggered. This invention periodically monitors registers and checks interrupt frequency and priority, and can also determine if null interrupts are being triggered. It utilizes the existing system interrupt resources of the instrument system to perform relevant logical processing on interrupts, preventing interrupt anomalies from causing system security problems and compensating for anomalies that cannot be detected by hardware or software watchdogs.

This invention belongs to the field of embedded software technology, specifically relating to a task scheduling method and system based on timer interrupt preemption. The method includes: creating task nodes and timer objects using a static creation method, and configuring priorities and scheduling times for tasks; constructing doubly linked lists of time series according to priorities based on a unified time base, and inserting task nodes into the corresponding linked lists in an orderly manner; setting timer interrupts of corresponding priorities according to the first task node of each linked list; responding to timer interrupts by triggering the execution of expired tasks, removing task nodes, and resetting timer interrupts; and utilizing processor interrupt priorities and context saving mechanisms during task execution to achieve preemption and recovery of high-priority tasks. This invention can reduce scheduling resource consumption and improve the scheduling orderliness and response timeliness of multi-priority tasks.

The invention discloses a real-time astronomical telescope control command transmission method based on a reflective memory network interruption mechanism. The method comprises the following steps: upgrading a unit subsystem of the TCS system; the method comprises the following steps: arranging reflection memory cards in independent computers of a telescope TCS, an OCS and a GSS to form a CETTN; a command-parameter decoupling storage architecture is designed, and decoupling of dynamic parameters and static execution logic is achieved through CETTN partition mapping; the interrupt priority is configured to be the highest level in the RTX system; when the transmitter writes a command ID to a specified address, the RFM card sends an interrupt request to the slave control machine; an interrupt service program ISR of a receiving end firstly reads the command ID, loads a corresponding parameter template from a pre-storage area, and transmits a parameter pointer to a control thread; and setting a timer under RTX, detecting ISR response time, entering a protection mode if the response time is too long, and abandoning the command and waiting for the next command if the CRC (Cyclic Redundancy Check) is failed.

The present invention provides an interrupt request method and a control device based on time overhead, belonging to the technical field of data processing, including: when a network communication device receives a message to be uploaded to the CPU, it parses the message and determines a switching condition according to the remaining time overhead of the current transaction, the execution interrupt switching time overhead, and the dynamic interrupt priority mechanism; if the message priority is higher than the current transaction priority or the remaining time overhead for completing the current transaction is greater than the execution interrupt switching time overhead, an interrupt request is generated to notify the CPU for processing; otherwise, after waiting for the CPU to complete the current transaction, an interrupt request is generated to notify the CPU for processing. Beneficial effects: Avoid the problem of low CPU utilization caused by the CPU frequently responding to interrupts and switching tasks when the network data traffic is large, and improve the CPU utilization while maintaining the real-time nature of the uploaded data.

The invention provides an interrupt control system. A gate module is used for receiving interrupt request signals sent by a plurality of interrupt sources; the level arbitration module is used for receiving the interrupt request signals sent by the gate module, performing importance level sorting on all the interrupt request signals, and sending the interrupt request signal with the highest importance level to the corresponding target processor; the interrupt priority queue module is provided with a first cache queue and a second cache queue, and the first cache queue is used for caching all current remaining interrupt request signals; and the second cache queue is used for caching the interrupt request signal with the highest importance level obtained by the level arbitration module at the next moment and the interrupt request signal with the higher importance level in the interrupt request signal with the highest importance level in the first cache queue, and sending the cached interrupt request signal to a corresponding target processor after the current interrupt is completed. The interrupt processing speed of the interrupt control system is high.

The apparatus includes an interrupt detection circuit for detecting a first interrupt to be handled by a processing circuit in a target execution environment. The apparatus also includes an exception notification circuit for notifying the processing circuit of an exception in response to the accepted interrupt. If the first interrupt meets at least one criterion, including if the target execution environment is not the active execution environment of the processing circuit, the exception notification circuit is configured to signal a first or second exception depending on an interrupt priority associated with the first interrupt. If the interrupt priority exceeds a threshold priority, the first exception is signaled to preemptively trigger a given action, where switching from the active execution environment to the target execution environment depends on the given action being performed. If the interrupt priority does not exceed the threshold priority, the second exception is signaled without preemptively triggering the given action.

The application provides a kind of interrupt processing method, device, electronic equipment and readable storage medium, it is related to computer technical field, method includes: obtaining the target virtual machine identification of target virtual machine sent by interrupt controller;The target virtual machine identification is the virtual machine identification corresponding to the interrupt identifier of target interrupt, and is obtained according to the target interrupt received by the interrupt controller, and the correspondence between pre-stored interrupt identifier and virtual machine identifier;If the target virtual machine identification is different from the virtual machine identification of the virtual machine being run in processor core, then the target interrupt priority of the target interrupt is obtained;If the target interrupt priority is higher than or equal to preset priority threshold, then through virtual machine management program, the virtual machine being run is switched to the target virtual machine, to process the target interrupt by the target virtual machine.Based on the application, virtual machine can be made to respond to interrupt quickly.

The invention discloses a single-chip microcomputer stack use limit evaluation method and device based on real-time interrupt sampling, a storage medium and an embedded system. The method comprises the steps that a periodic interrupt source with the highest interrupt priority is set / called; directly reading an instantaneous value of a hardware stack pointer register when the execution of the service program with the highest priority interruption is finished; comparing the read instantaneous value of the stack pointer with a dynamically maintained historical minimum value of the stack pointer; updating the historical minimum value of the stack pointer according to the growth direction of the stack memory; and based on the updated historical minimum value of the stack pointer and the initial address of the stack memory, calculating to obtain a historical use peak value of the stack memory. According to the method, the instantaneous value of the stack pointer register is read when the interruption occurs, so that an accurate measurement result is obtained, and all security risks introduced by writing and detecting memory contents are eradicated. As only the historical minimum value of the stack pointer needs to be dynamically maintained, an accurate measurement result can be obtained under the condition of low performance resource cost.

The present invention relates to the technical field of system-on-chip (SoC) service interrupt processing, and specifically to a SoC interrupt processing method based on a hardware sequencer, comprising: pre-programming an interrupt processing instruction sequence into an instruction RAM, and configuring the instruction set, sequence processor, and interrupt priority policy of a task scheduler sequencer; the task scheduler sequencer receives an interrupt signal and selects a corresponding sequence processor based on the interrupt type; for low-priority interrupts, the task scheduler sequencer directly executes a pre-stored instruction sequence to complete the interrupt response; for high-priority interrupts, the task scheduler sequencer caches register status and sends a message packet to notify the CPU for collaborative processing. The present invention implements autonomous interrupt response through a hardware sequencer, with zero CPU intervention for low-priority interrupts and a lightweight message mechanism for high-priority interrupts, thereby improving efficiency while reducing bandwidth usage and power consumption.

The invention discloses an interrupt nesting preemption method and system oriented to a power internet of things operating system. The method comprises the following steps: constructing a unified priority scheduling protocol core; receiving a task request and / or a hardware interrupt request through a unified priority scheduling protocol core; obtaining a current execution priority corresponding to the current executor, and obtaining a task priority corresponding to the task request and / or an interrupt priority corresponding to the hardware interrupt request through a unified priority scheduling protocol core; according to the level relation between the task priority and the current execution priority and the resource waiting state of the task request, active chain type redirection processing is carried out through a unified priority scheduling protocol core; and executing a corresponding response operation through a unified priority scheduling protocol core according to a level relationship between the interrupt priority and the current execution priority. The method can meet strict requirements of a power control scene on real-time performance and reliability, and can be widely applied to the technical field of power.

The present invention provides a dynamic adaptive interrupt processing method and system. The method comprises: real-time acquisition of multiple operating status parameters of each peripheral module in a processor, evaluating the interrupt priority of each interrupt based on a priority evaluation model; predicting the number of triggers of each interrupt in a future time period based on the historical trigger count of each interrupt based on a prediction algorithm; determining an interrupt scheduling strategy based on the interrupt priority of each interrupt and the number of triggers in the future time period; regularly evaluating the efficiency of the interrupt scheduling strategy, and adjusting the parameters of the priority evaluation model and the prediction algorithm based on the evaluation results to adjust the interrupt scheduling strategy. Through the present invention, the priority of each interrupt can be adjusted in real time based on the operating status parameters of the peripheral module, and a corresponding interrupt scheduling strategy can be generated. The method is suitable for performance-constrained scenarios where MCU resources are limited, real-time requirements are high, and power consumption requirements are high.

Systems, computer program products, and methods are described herein for determining and resolving interruptions to computing components. The present disclosure is configured to identify an interruption(s) and a potential response computing component(s); generate a Bi-Partite knowledge graph comprising the interruption(s) within a interruption priority queue(s) and the potential response computing component(s) within a response priority queue(s), wherein the Bi-Parte knowledge graph comprises a relational edge between the interruption priority queue(s) and the response priority queue(s); dynamically update the Bi-Partite knowledge graph with the interruption priority queue(s) based on an interruption factor(s) and the response priority queue(s) based on potential response factor(s); select, based on the updated interruption priority queue(s) and the updated response priority queue(s), a priority interruption and a priority potential response computing component; and resolve the priority interruption with the priority response computing component.

The invention discloses a vehicle-mounted code fault diagnosis method and device, and the method comprises the steps: extracting semantic features of a target code segment from a code feature sequence of a vehicle-mounted source code, and obtaining target features; performing dynamic position coding on the vehicle-mounted source code, constructing a time sequence constraint feature according to a coding result, and constructing an interrupt priority graph based on the target feature and the time sequence constraint feature; generating a target fault tree based on the interrupt priority graph and a pre-constructed resource competition relationship network; the target fault tree comprises an event node set, a gating event edge set and a node fault probability, and the node fault probability is determined by a connection weight of an interrupt priority graph and a connection weight of a resource competition network; and the fault mode-influence analysis table is generated based on the target fault tree, and fault diagnosis is performed according to the fault mode-influence analysis table, so that the comprehensiveness and accuracy of fault identification and diagnosis of the vehicle-mounted code can be improved.

The invention belongs to the field of software model detection, and relates to a correctness verification method for a serialization-based unbounded interrupt driver. An interrupt driving program is converted into a sequenced program by using a sequenced technology, global auxiliary variables such as a program counter, a control mode variable and a shielding variable are introduced, random context switching, multi-stage interrupt nesting and interrupt shielding behaviors are simulated by means of macro and execution modes, and the obtained sequenced program is detected by using a model detection tool CBMC or CPAchecker. And verifying the correctness of the unbounded interrupt driver. According to the method, an interrupt driving program is converted into an equivalent sequential execution program, and all possible execution interlaced paths are accurately simulated, so that the correctness of the program can be effectively verified, and particularly under the condition of complex behaviors such as interrupt nesting, multi-stage interrupt, priority scheduling and interrupt shielding, the execution efficiency of the program is greatly improved. And the problems of state space explosion and false positive in a traditional model detection method can be avoided.

The invention provides a dynamic self-adaptive interrupt processing method and system, and the method comprises the steps: collecting a plurality of working state parameters of each peripheral module in a processor in real time, and evaluating the interrupt priority of each interrupt based on a priority evaluation model; according to the historical triggering times of each interrupt, predicting the triggering times of each interrupt in a future time period based on a prediction algorithm; determining an interrupt scheduling strategy according to the interrupt priority of each interrupt and the triggering times in the future time period; and regularly evaluating the efficiency of the interrupt scheduling strategy, and adjusting parameters of the priority evaluation model and the prediction algorithm according to an evaluation result so as to adjust the interrupt scheduling strategy. According to the method and the device, the priority of each interrupt can be adjusted in real time according to the working state parameters of the peripheral module, the corresponding interrupt scheduling strategy is given, and the method and the device are suitable for scenes with limited performance under the conditions of MCU resource shortage, high real-time performance requirement and high power consumption requirement.

The application discloses a low-delay interrupt processing method and system of an intelligent control center, and belongs to the field of industrial control computer system architecture. The method comprises the following steps: analyzing an interrupt request to obtain an event type identifier; matching the event type identifier to a corresponding interrupt priority based on a predefined event priority mapping table; selecting a path from a set of pre-allocated and physically isolated hardware response paths according to the interrupt priority; distributing the interrupt request and context data to a pre-bound processing core through the selected path; and executing a preloaded simplified processing routine by the processing core to generate a driving instruction. The application combines event semantic mapping with physically isolated hardware paths to provide a deterministic low-delay response channel for core emergency interrupts, and improves system reliability through a load balancing mechanism based on cache consistency, effectively solving the problem of large interrupt processing delay jitter in high-concurrency industrial intelligent control centers, and significantly improving the real-time performance of the control system.

The present invention provides a photovoltaic inverter system interrupt control method and device, as well as a photovoltaic system. The photovoltaic inverter system includes a control module, an inverter module, and multiple photovoltaic modules, wherein the control module includes an EPWM module. The method comprises: assigning corresponding interrupt processing content to each EPWM module based on the number of photovoltaic modules and the number of EPWM modules; determining the interrupt priority of each EPWM module and the interrupt triggering time of each type of interrupt processing content corresponding to each EPWM module based on the interrupt processing content corresponding to each EPWM module; and setting parameters for each EPWM module based on the interrupt priority and the interrupt triggering time, so that each EPWM module performs interrupt control of the photovoltaic inverter system according to the interrupt priority and the interrupt triggering time. When a DSP chip is updated, the present invention can effectively utilize the EPWM module of the newly adopted DSP chip to implement interrupt control of the photovoltaic inverter system.

The application provides a kind of energy storage system control method and energy storage system based on interrupt task, the unassigned interrupt vector of processor in energy storage system is configured as target interrupt vector, and the interrupt priority of target interrupt vector is set as the highest priority of system;When detecting that any energy storage device in energy storage system appears preset emergency event, target interrupt vector is triggered, so that processor jumps to execute target interrupt service program pointed by target interrupt vector;Wherein, target interrupt service program is used to process emergency event of energy storage device, and target interrupt service program execution process cannot be preempted by other interrupt program.By configuring unassigned interrupt vector of processor as target interrupt vector with highest priority, the fast processing of emergency event can be realized without affecting other processes, and the service program is not preempted by other interrupts due to the highest priority feature, so that the emergency task is completed efficiently without delay.

A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.