8 results about "Race condition" patented technology

The application provides a resource lock configuration method, device, storage medium and program product, and relates to the technical field of vehicle software. The method comprises the following steps: in response to detecting a resource lock configuration instruction, obtaining a task white list, the task white list containing a task in which an application program related to processor sleep and wake is located; in the task white list, determining that a task that has a race condition resource use risk relative to a first task is a second task, the first task being a task in which a processor sleep and wake processing program is located; and configuring a resource lock for the first task and the second task. The application can improve the resource lock configuration efficiency and accuracy.

The present application provides a secure data penetration testing method, including: pre-establishing a multi-threaded application race condition vulnerability feature library, performing static analysis on the source code of the target application to identify potential race condition vulnerability points and obtaining a preliminary set of vulnerability candidates; for the monitored suspected race condition events, abstracting the event context information into constraint conditions, using a constraint solver to explore the input combinations of the suspected static conditions, and determining the minimum input set that stably triggers the race condition; for the memory models and synchronization primitives of different programming languages, obtaining race condition anti-patterns and extracting general exploitation primitives covering various race condition vulnerabilities; during the penetration testing process, applying static analysis, dynamic monitoring, and symbolic execution to mine race condition vulnerabilities in the target application system, verifying the exploitability of the vulnerabilities, and assisting in completing the evaluation of the system security.

The present invention discloses a real-time simulation performance evaluation method based on an ARMv8 architecture multi-core processor, specifically relating to the technical field of multi-core performance evaluation; it includes the following steps: setting up a concurrent monitoring module to collect the access instruction sequence and memory barrier instruction information of the processing core; analyzing the address cross-relationship and timing dependency between access instructions to generate an instruction reordering risk access group; performing concurrent consistency analysis on the risk access group to identify race conditions and record the synchronization method and memory barrier instruction distribution; injecting high-intensity concurrent operations in the simulation environment, continuously tracking the read and write operations of shared variables, and analyzing the instruction execution order; counting the matching degree under different simulation load conditions to generate a real-time simulation performance evaluation index for the weak memory model, which can accurately identify potential consistency problems caused by instruction reordering.

The invention discloses a historical debugging-oriented multi-thread race condition accurate reproduction method, which comprises the following steps of: establishing a semantic equivalence mapping table of a synchronization instruction between different target architectures by defining three causal relationships of release acquisition, wake-up execution and memory visibility, recording a user mode and kernel mode synchronization event when a first target architecture executes a target program, and replaying the user mode and kernel mode synchronization event when the first target architecture executes the target program. A bidirectional causal chain with confidence is constructed in combination with causal conditions, a replay engine is started in a second target architecture during replay, synchronization operation is recognized and matched with an original synchronization event in the semantic equivalence mapping table and the causal chain, the semantic reproduction state of a core dependency event is verified, and the core dependency event is replayed; and forcibly reproducing a memory, a state flag, a memory barrier and a thread state according to records by neglecting hardware actual execution, finally adding subsequent events into a queue according to confidence, and completing semantic reproduction of the subsequent events according to a recorded information sequence, so that accurate reproduction of a target program execution process under a multi-thread race condition is realized.

The present disclosure relates to a method and a system for handling race condition in a communication network The disclosure encompasses receiving, at a Converged Charging Function (CHF) [132] from a Policy Control Function (PCF) [122], a Spending Limit Request (SLR request) and transmitting, from the CHF [132] to an Online Charging System (OCS) [308], the SLR request. The disclosure further encompasses receiving, at the CHF [132] from the OCS [308], a successful Spending Limit Response (SLR response) based on the SLR request and initiating, at the CHF [132], a network session based on the successful SLR response. The disclosure further encompasses maintaining, the network session at the CHF [132]; receiving, at the CHF [132], a session termination request (STR request) from the PCF [122] and releasing, at the CHF [132], the network session based on the STR request from the PCF [122].

A system and method for data synchronization in a circular buffer architecture is disclosed. Embodiments describe a data synchronization mechanism, focusing on the efficient management of the circular buffer between producer and consumer processes. In an embodiment, a method uses a lapping technique to facilitate parallel processing without the need for locking mechanisms, ensuring continuous data flow and real-time responsiveness. Further, the method uses modulated lap indicators and associated paperclip indicators at each buffer slot to track access history and resolve race conditions. The method determines valid access sequences through indicator comparison, enabling reliable conflict resolution, computes warp distances to guide synchronization updates, and dynamically adjusts buffer configurations in response to system events. The method also preserves access states across interrupts or context switches, enabling seamless continuation of operations. The method provides a lock-free synchronization mechanism that enables precise state tracking and efficient coordination of concurrent buffer access.

A system and method for data synchronization in a circular buffer architecture is disclosed. Embodiments describe a data synchronization mechanism, focusing on the efficient management of the circular buffer between producer and consumer processes. In an embodiment, a method uses a lapping technique to facilitate parallel processing without the need for locking mechanisms, ensuring continuous data flow and real-time responsiveness. Further, the method uses modulated lap indicators and associated paperclip indicators at each buffer slot to track access history and resolve race conditions. The method determines valid access sequences through indicator comparison, enabling reliable conflict resolution, computes warp distances to guide synchronization updates, and dynamically adjusts buffer configurations in response to system events. The method also preserves access states across interrupts or context switches, enabling seamless continuation of operations. The method provides a lock-free synchronization mechanism that enables precise state tracking and efficient coordination of concurrent buffer access.

This invention discloses a method for accurately reproducing multi-threaded race conditions for historical debugging. By defining three types of causal relationships—release acquisition, wake-up execution, and memory visibility—a semantic equivalence mapping table of synchronization instructions between different target architectures is constructed. Then, when the target program is executed on the first target architecture, user-mode and kernel-mode synchronization events are recorded. Combined with causal conditions, a bidirectional causal chain with confidence is constructed. During replay, a replay engine is started on the second target architecture. First, the synchronization operation is identified and matched with the original synchronization events in the semantic equivalence mapping table and the causal chain. The semantic reproduction status of core dependent events is verified. Ignoring actual hardware execution, memory, status flags, memory barriers, and thread states are forcibly reproduced according to the records. Finally, subsequent events are added to the queue according to the confidence level, and the semantic reproduction of subsequent events is completed in the order of the recorded information. This achieves accurate reproduction of the target program execution process under multi-threaded race conditions.