23 results about "Boundary scan" patented technology

The invention discloses a virtual power plant time-of-use electricity price dynamic optimization method and system, and the method comprises the steps: recognizing a power fluctuation component through obtaining distributed resource power time sequence data and a user response record, generating a price sensitivity coefficient, and constructing an elastic response space reflecting the user response potential; performing boundary scanning on the elastic response space to generate a schedulable capacity envelope, setting a trigger threshold along the envelope, and reversely deriving an energy storage intervention opportunity to form a time-sharing scheduling strategy; projecting the power grid dispatching price to an elastic space, cutting off based on a power balance requirement, and determining a price floating range; searching a user response path in the range, identifying a response intensity change inflection point, evaluating stability, and generating a price anchor point; performing time interval analysis on the anchor points to obtain a price ramp rate and a change speed, and extracting a synchronization rate index of group response behaviors; and comparing the synchronization rate with a target value to generate an optimized price sequence, thereby realizing dynamic adaptive adjustment of the time-of-use electricity price.

This invention discloses a chip layout image generation method based on a boundary tracking scan line algorithm. By designing a sub-image-polygon data structure and establishing a maximum matrix of adjacent polygons in the sub-image, this method improves the boundary scan line algorithm to quickly segment the complete chip layout into sub-images and generate corresponding binary images. The algorithm designs a sub-image bounding box-polygon bounding box data structure to quickly locate which polygons are most likely to intersect with the sub-image. Saving this data constructs the maximum bounding box of all polygons contained in the current sub-image, eliminating the need for the algorithm to calculate the intersection points of polygons with the sub-image, thus reducing the time consumption for intersection point calculation. Furthermore, a boundary tracking method is designed to improve the scan line algorithm. By saving each point in the boundary, when scanning a row, it is not necessary to calculate the intersection points of the scan line and the polygon boundary, further reducing the algorithm complexity.

A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.

The present disclosure relates to a method of debugging a printed circuit board having at least one boundary-scan compliant device, the method using an electronic processing unit and comprising the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the boundary-scan compliant device comprising a list of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; selecting and displaying a circuit diagram of at least a portion of the device mounted on the printed circuit board, the circuit diagram comprising at least one device of a plurality of devices mounted on the printed circuit board and at least one other device of the plurality of devices, the other device comprising circuit terminals that are interconnected with circuit terminals of the device for visualizing at least the device, the other device and the interconnections. The present disclosure also relates to a corresponding debugging apparatus and to a corresponding computer program product.

A boundary-scan standard pin test system is disclosed. In the system, to-be-tested slots are electrically connected to form different to-be-tested series chains, or riser cards which are inserted into the to-be-tested slots are electrically connected to each other through first boundary-scan input interfaces and first boundary-scan output interfaces thereof or through second boundary-scan input interfaces and second boundary-scan output interfaces thereof, to form different riser-card series chains; a TAP controller provides a boundary-scan format test signal to a to-be-tested series chain or a riser-card series chain to make a test card perform a boundary-scan standard pin test, so as to achieve the technical effect of efficiency of providing the boundary-scan standard pin test for the to-be-tested slots on different to-be-tested boards by a testing machine.

This invention relates to a aging and screening device for antifuse-type FPGA devices, comprising a data stream generation module, an aging driver board, and an aging station board. The data stream generation module is implemented using Matlab software and generates an excitation JTAG data stream file through program design and algorithm iteration. The data stream generation module communicates with the aging driver board via a digital channel; the aging driver board and the aging station board are connected via a dedicated interface. This invention configures the serial data stream through a JTAG boundary scan port and is equipped with a large-capacity test code storage space and multiple programmable analog channels, providing and real-time monitoring of the device's operating voltage and current, as well as the device's operating status. It can meet the hardware resource and bit stream capacity requirements of antifuse-type FPGA devices of different types and sizes in aging and screening, and has wide applicability.

Integrated circuit devices, methods, and circuitry for configuring input / output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.

An embodiment of an integrated circuit may comprise first circuitry to provide a boundary scan of a signal of the integrated circuit, wherein the first circuit includes an input test data signal and an output test data signal, and second circuitry coupled to the first circuitry to selectively output one of the input test data signal and the output test data signal. Other embodiments are disclosed and claimed.

This invention discloses a configurable parallel test circuit and method for a three-dimensional stacked packaged chip. The test circuit includes configurable boundary scan unit pairs. The three-dimensional stacked packaged chip has multiple layers of small dies. Each configurable boundary scan unit pair includes a first configurable boundary scan unit for connecting to the input port of the small die and a second configurable boundary scan unit for connecting to the output port of the small die. The first and second configurable boundary scan units are configured into different modes through different control signals. Multiple configurable boundary scan unit pairs are set on each layer of small dies, and the multiple configurable boundary scan unit pairs on each layer of small dies are connected in series according to different modes. The configurable boundary scan unit pairs on adjacent layers of small dies are cascaded. The advantages of this invention are: flexible configuration of the number of scan chains, which is beneficial to practical applications, and low manufacturing cost.

This invention relates to the field of internal circuit testing technology for airborne equipment, specifically a boundary scan-based testing method for 659 bus input boards. The method includes: Step 1, designing the 659 bus main control board and test resource boards, designing the timing and control logic, and the industrial computer test control program; Step 2, connecting the 659 bus main control board, test resource boards, boundary scan controller, and industrial computer, and connecting the 659 bus main control board, test resource boards, and boundary scan controller to the board under test; Step 3, performing 659 bus testing; Step 4, performing input acquisition testing, including AD conversion testing and discrete input testing; Step 5, performing self-test functionality testing. This invention enables rapid fault location of 659 bus input boards, significantly reducing waste in the production process, saving resources, and lowering costs; it also features a simple structure, reliable operation, and strong applicability; and improves the testing and maintenance capabilities of airborne products.

The invention discloses a method for constructing a curved surface heat flux density boundary by using a scanning electron beam, which comprises the following steps of: discretizing the target curved surface heat flux density boundary, performing space division by adopting a uniform grid, and positioning an electron beam scanning point at the central position of each grid unit; setting a reference surface; acquiring a surface movement track of the electron beam on the curved surface heat flux density boundary; obtaining a projection point of each scanning point on the reference surface; calculating the electron beam power of the electron beam at the curved surface heat flux density boundary scanning point; calculating the target heat flux density of each projection point; and obtaining residence time distribution of the electron beam on different scanning points. The method can be suitable for a plane and a curved surface at the same time, the curved surface heating problem is converted into the plane heating problem, the residence time distribution is solved, meanwhile, the corresponding relation between the electron beam deflection angle corresponding to each scanning point and the current in the deflection coil is obtained, and electromagnetic control parameters of electron beams can be directly given based on a target heat flux density field; and the scanning electron beam heating experiment is directly guided.

The invention discloses a daisy chain removal processing system and method suitable for a server mainboard DDR connector boundary scan test. The system comprises at least one boundary scanning controller and an upper computer which is in real-time communication with the boundary scanning controller; the boundary scan controller is electrically connected with the mainboard CPU to be tested through at least one group of JTAG interfaces; a DDR connector on the mainboard to be tested is in butt joint with a plurality of DDR simulation test cards through golden fingers; a first control chip is arranged in the DDR simulation test card; a preset communication interface is electrically connected with an input or output pin of a to-be-tested mainboard CPU, real-time test instruction and data interaction work is achieved, a traditional JTAG daisy chain architecture is replaced with an I2C bus, various test signals are innovatively collected to a detectable pin of the CPU through a current-limiting resistance network, unified collection of test responses is achieved, and the test efficiency is improved. The problem of whole chain interruption caused by a single-point fault is solved, the reliability of a test system is improved, the jig structure is simplified, and the maintenance efficiency is improved.

The embodiment of the application discloses a pin state control method and system of a chip, a chip and an upper computer, relates to the technical field of chips, and can effectively improve the design efficiency and integration of the chip. The method comprises the following steps: generating an enable control signal of an input-output control component corresponding to a target pin of the chip based on preset values moved into a boundary scan unit corresponding to the target pin through a JTAG interface; and controlling the input-output control component to be in an input enable state or an output enable state according to the enable control signal, so that, in the input enable state, a pin signal flows into the chip through the target pin, or in the output enable state, a pin signal flows out of the chip through the target pin. The application is suitable for being applied to the chip.

The application relates to the technical field of automatic driving car simulation, in particular to a kind of end-to-end big model two-way failure boundary scanning and hysteresis effect evaluation method and equipment.The method comprises the following steps: different intensity failure factors in limit failure scene factor library are generalized and combined to obtain different limit failure scenes;end-to-end intelligent driving big model is tested;hysteresis coefficient is calculated according to failure threshold and recovery threshold;the bottom strategy of end-to-end intelligent driving big model after failure is determined according to the size of hysteresis coefficient.The application calculates hysteresis coefficient to quantify system recovery capability, which helps to promote the algorithm progress of driving big model.

The application provides a RISC-V processor download debugging method and system based on an FPGA-JTAG interface, and the method comprises the following steps: based on a boundary scan register address and a bit width, modifying boundary scan configuration code related to an FPGA chip in host computer source code; based on the boundary scan register, modifying the cfg configuration code of the host computer to be configured as a boundary scan mode; constructing a data packet containing a boundary scan register address, a debugging instruction and debugging data by the host computer, and transmitting the data packet to a data parsing module through an FPGA-JTAG interface; according to the data packet format, analyzing a TDI signal, and switching a TAP state machine state through a control TMS signal to realize the debugging of the RISC-V processor. The application realizes the debugging by multiplexing the FPGA-JTAG interface, improves the debugging efficiency and reliability, simplifies the hardware design, and reduces the system cost.

A wafer-scale 3D stacked inference engine integrates stacked logic die and stacked memory die on a unitary silicon substrate with an on-silicon interconnect fabric to execute neural-network models using low-precision arithmetic. Compute chiplets and high-bandwidth memory stacks are coupled across reticle-stitched interconnect regions that form a single all-silicon domain. A redistribution-layer network provides ultra-short-reach links and express lanes for inter-region data movement while a control subsystem issues tile-level schedules that overlap compute and transfer. Wafer-integrated power delivery and microchannel cooling support high density operation, and test access structures enable loopback and boundary-scan verification of stacked connections. The architecture reduces multi-hop latency, improves energy efficiency, and allows large models to be inferenced at wafer scale without leaving the all-silicon domain.

A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.

This invention discloses a method and system for dynamic optimization of time-of-use pricing in virtual power plants. By acquiring distributed resource power time-series data and user response records, it identifies power fluctuation components and generates price sensitivity coefficients, constructing an elastic response space reflecting user response potential. Boundary scanning of the elastic response space generates a dispatchable capacity envelope; trigger thresholds are set along the envelope, and the timing of energy storage intervention is derived in reverse, forming a time-of-use scheduling strategy. The grid dispatch price is projected onto the elastic space and truncated based on power balance requirements to determine the price fluctuation range. Within this range, user response paths are searched, inflection points of response intensity changes are identified, and stability is evaluated to generate price anchor points. Time interval analysis is performed on the anchor points to obtain price ramp-up rates and change rates, extracting synchronization rate indicators of group response behavior. The synchronization rate is compared with the target value to generate an optimized price sequence, achieving dynamic adaptive adjustment of time-of-use pricing.

The invention relates to an asset management method and system based on RFID, a storage medium and electronic equipment, and relates to the technical field of data processing, and the method comprises the steps: obtaining at least one warning region in a goods warehouse, the warning region being a region where goods are liable to be lost in the goods warehouse; if the RFID tag of at least one actual goods is scanned through a preset RFID card reader, the early warning level for early warning is determined based on the actual goods type of each actual goods, the preset RFID card reader is an RFID card reader for scanning the RFID tag located on the boundary of an actual area, and the actual area is a warning area where the RFID tag is scanned at the boundary at present; the actual goods are goods stored in the actual area; and according to the early warning level, corresponding early warning information is sent for the actual area. The method and the device have the effect of improving the early warning timeliness when the assets in the warehouse are monitored.

The application discloses a cross-circuit-board boundary scan chain generation method, characterized by comprising the following steps: obtaining a to-be-tested chip which has created a pin library and adding the to-be-tested chip to a testable chip list; in a traversal process, other testable chips upstream of a current testable chip are found along a TDI of the current testable chip, and other testable chips downstream of the current testable chip are found along a TDO of the current testable chip, and the testable chips found are sequenced in an order from upstream to downstream; according to a test requirement, testable chips of the same type in the testable chip list are connected in series according to the testable chip sequencing to form an executable scan chain; a TDI of the executable scan chain is the TDI of the first scan chain before being connected in series, a TDO of the executable scan chain is the TDO of the nth scan chain before being connected in series, and n>1. The application can reduce port resource occupation and improve test efficiency under the condition of limited hardware resources and without reducing test coverage.

The invention discloses a test method for optimizing an integrated circuit in CoWoS packaging, and relates to the technical field of function testing, virtualized integration of test resources is achieved by constructing a reconfigurable virtual test unit, and the reconfigurable virtual test unit can be used for testing the integrated circuit in the CoWoS packaging by multiplexing an inherent function logic circuit in a chip. An independent physical test circuit does not need to be additionally arranged in a silicon adapter plate or a chip, a control word is issued through a bus, a function logic circuit is triggered to be dynamically switched between a normal working mode and a test mode, and only special functions such as test signal generation, verification or resistance detection are undertaken in the test mode; according to the design, the occupation of a special test circuit on silicon resources is directly avoided, the wiring and bonding pad requirements related to testing are reduced, meanwhile, the original high-performance characteristic of the functional logic circuit is utilized, online monitoring on the integrity of high-speed interconnection signals is achieved, fault types, such as crosstalk and jitter, which cannot be covered by traditional boundary scanning can be accurately captured, and the fault detection accuracy is improved. And dual optimization is formed from hardware resource utilization and test coverage dimensions.

The embodiment of the utility model relates to the technical field of chips, and discloses a signal generation circuit, a boundary scanning unit, a circuit and electronic equipment, and the signal generation circuit outputs a first level signal through two input OR gate modules, and outputs a second IO signal through a first data triggering module. A first data trigger module is used for outputting a first level signal, a three-input OR gate module is used for outputting a second level signal, a second data trigger module is used for outputting a selection signal, and a first IO signal input to a two-input OR gate module is set as a high level signal, so that the first level signal is the high level signal, and the second level signal is the high level signal; according to the technical scheme, the selection signal is enabled to be a high-level signal, and when the selection signal is the high-level signal, the IO state of the IO unit is controlled by the boundary scanning unit, so that the IO state of the IO unit can be maintained under the condition that the JTAG switches the IR instruction, and the use scene of the JTAG is expanded.

The present invention discloses a method for identifying and tracking the boundaries of meteorological satellite convective clouds, comprising the following steps: reading meteorological satellite grid point data and representing it according to a certain data structure; formulating grid point encoding rules and effectively encoding each grid point; identifying and tracking each grid point according to an algorithm to ensure that it belongs to a storm cloud cluster; performing boundary scanning on the storm cloud cluster to obtain its boundary point set; the final result is a cloud cluster set containing several cloud clusters, each cloud cluster having a number, a boundary, and grid points that constitute the cloud cluster, and each grid point self-contained with spatial and physical properties. The meteorological satellite convective cloud cluster identification and boundary tracking method provided by the present invention is no longer limited to image grayscale recognition, but implements a feature recognition and boundary tracking method for a regular grid field; it can obtain full information data on the spatial and physical properties of each grid point, providing data support for refined data analysis.