11 results about "Boundary scan" patented technology

A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.

The present disclosure relates to a method of debugging a printed circuit board having at least one boundary-scan compliant device, the method using an electronic processing unit and comprising the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the boundary-scan compliant device comprising a list of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; selecting and displaying a circuit diagram of at least a portion of the device mounted on the printed circuit board, the circuit diagram comprising at least one device of a plurality of devices mounted on the printed circuit board and at least one other device of the plurality of devices, the other device comprising circuit terminals that are interconnected with circuit terminals of the device for visualizing at least the device, the other device and the interconnections. The present disclosure also relates to a corresponding debugging apparatus and to a corresponding computer program product.

Integrated circuit devices, methods, and circuitry for configuring input / output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.

An embodiment of an integrated circuit may comprise first circuitry to provide a boundary scan of a signal of the integrated circuit, wherein the first circuit includes an input test data signal and an output test data signal, and second circuitry coupled to the first circuitry to selectively output one of the input test data signal and the output test data signal. Other embodiments are disclosed and claimed.

This invention discloses a configurable parallel test circuit and method for a three-dimensional stacked packaged chip. The test circuit includes configurable boundary scan unit pairs. The three-dimensional stacked packaged chip has multiple layers of small dies. Each configurable boundary scan unit pair includes a first configurable boundary scan unit for connecting to the input port of the small die and a second configurable boundary scan unit for connecting to the output port of the small die. The first and second configurable boundary scan units are configured into different modes through different control signals. Multiple configurable boundary scan unit pairs are set on each layer of small dies, and the multiple configurable boundary scan unit pairs on each layer of small dies are connected in series according to different modes. The configurable boundary scan unit pairs on adjacent layers of small dies are cascaded. The advantages of this invention are: flexible configuration of the number of scan chains, which is beneficial to practical applications, and low manufacturing cost.

The invention discloses a daisy chain removal processing system and method suitable for a server mainboard DDR connector boundary scan test. The system comprises at least one boundary scanning controller and an upper computer which is in real-time communication with the boundary scanning controller; the boundary scan controller is electrically connected with the mainboard CPU to be tested through at least one group of JTAG interfaces; a DDR connector on the mainboard to be tested is in butt joint with a plurality of DDR simulation test cards through golden fingers; a first control chip is arranged in the DDR simulation test card; a preset communication interface is electrically connected with an input or output pin of a to-be-tested mainboard CPU, real-time test instruction and data interaction work is achieved, a traditional JTAG daisy chain architecture is replaced with an I2C bus, various test signals are innovatively collected to a detectable pin of the CPU through a current-limiting resistance network, unified collection of test responses is achieved, and the test efficiency is improved. The problem of whole chain interruption caused by a single-point fault is solved, the reliability of a test system is improved, the jig structure is simplified, and the maintenance efficiency is improved.

The embodiment of the application discloses a pin state control method and system of a chip, a chip and an upper computer, relates to the technical field of chips, and can effectively improve the design efficiency and integration of the chip. The method comprises the following steps: generating an enable control signal of an input-output control component corresponding to a target pin of the chip based on preset values moved into a boundary scan unit corresponding to the target pin through a JTAG interface; and controlling the input-output control component to be in an input enable state or an output enable state according to the enable control signal, so that, in the input enable state, a pin signal flows into the chip through the target pin, or in the output enable state, a pin signal flows out of the chip through the target pin. The application is suitable for being applied to the chip.

The application relates to the technical field of automatic driving car simulation, in particular to a kind of end-to-end big model two-way failure boundary scanning and hysteresis effect evaluation method and equipment.The method comprises the following steps: different intensity failure factors in limit failure scene factor library are generalized and combined to obtain different limit failure scenes;end-to-end intelligent driving big model is tested;hysteresis coefficient is calculated according to failure threshold and recovery threshold;the bottom strategy of end-to-end intelligent driving big model after failure is determined according to the size of hysteresis coefficient.The application calculates hysteresis coefficient to quantify system recovery capability, which helps to promote the algorithm progress of driving big model.

A wafer-scale 3D stacked inference engine integrates stacked logic die and stacked memory die on a unitary silicon substrate with an on-silicon interconnect fabric to execute neural-network models using low-precision arithmetic. Compute chiplets and high-bandwidth memory stacks are coupled across reticle-stitched interconnect regions that form a single all-silicon domain. A redistribution-layer network provides ultra-short-reach links and express lanes for inter-region data movement while a control subsystem issues tile-level schedules that overlap compute and transfer. Wafer-integrated power delivery and microchannel cooling support high density operation, and test access structures enable loopback and boundary-scan verification of stacked connections. The architecture reduces multi-hop latency, improves energy efficiency, and allows large models to be inferenced at wafer scale without leaving the all-silicon domain.

The application discloses a cross-circuit-board boundary scan chain generation method, characterized by comprising the following steps: obtaining a to-be-tested chip which has created a pin library and adding the to-be-tested chip to a testable chip list; in a traversal process, other testable chips upstream of a current testable chip are found along a TDI of the current testable chip, and other testable chips downstream of the current testable chip are found along a TDO of the current testable chip, and the testable chips found are sequenced in an order from upstream to downstream; according to a test requirement, testable chips of the same type in the testable chip list are connected in series according to the testable chip sequencing to form an executable scan chain; a TDI of the executable scan chain is the TDI of the first scan chain before being connected in series, a TDO of the executable scan chain is the TDO of the nth scan chain before being connected in series, and n>1. The application can reduce port resource occupation and improve test efficiency under the condition of limited hardware resources and without reducing test coverage.

The invention discloses a test method for optimizing an integrated circuit in CoWoS packaging, and relates to the technical field of function testing, virtualized integration of test resources is achieved by constructing a reconfigurable virtual test unit, and the reconfigurable virtual test unit can be used for testing the integrated circuit in the CoWoS packaging by multiplexing an inherent function logic circuit in a chip. An independent physical test circuit does not need to be additionally arranged in a silicon adapter plate or a chip, a control word is issued through a bus, a function logic circuit is triggered to be dynamically switched between a normal working mode and a test mode, and only special functions such as test signal generation, verification or resistance detection are undertaken in the test mode; according to the design, the occupation of a special test circuit on silicon resources is directly avoided, the wiring and bonding pad requirements related to testing are reduced, meanwhile, the original high-performance characteristic of the functional logic circuit is utilized, online monitoring on the integrity of high-speed interconnection signals is achieved, fault types, such as crosstalk and jitter, which cannot be covered by traditional boundary scanning can be accurately captured, and the fault detection accuracy is improved. And dual optimization is formed from hardware resource utilization and test coverage dimensions.