323 results about "Boundary scan" patented technology

A mechanism for enabling compliance with the IEEE boundary-scan standard 1149.1 includes, in a first preferred embodiment, a compliance enabler working with non-compliant embedded boundary-scan cells to enable a Device Under Test (DUT) to function as an IEEE-standard-compliant part, thus allowing full utilization of existing test tool generation and operation of the IEEE standard. The enabler is preferably provided separately from boundary scan-cells embedded in core logic designs. The enabler includes a Test Access Port (TAP) controller and related decoding circuits to generate necessary compliance signals based on various conventional TAP controller variables and instruction functions. The embedded boundary-scan cells preferably include an internal scan cell architecture. In a second embodiment, a second enabler works with a TAP emulator to allow testing of TAP-less DUTs.

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

A boundary scan cell includes a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output. The data output of the shift latch is coupled to the data input of the update latch. The boundary scan cell further includes control circuitry that controls operation of the flushable latch circuit. The control circuitry selects, as input data for the flushable latch, one of a functional logic signal and a boundary scan signal in response to a mode signal. If the mode signal indicates a test mode, the control circuitry selects the boundary scan signal as the input data and causes the flushable latch to flush through the input data to the data output of the flushable latch independent of a system clock signal. The boundary scan cell can be implemented as either an input or output cell and preferably is compliant with IEEE Std 1149.1.

A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.

A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.

JTAG operations are carried out remotely over a network interface. The host processor includes a JTAG interpreter and a host side JTAG driver. A target device includes a target side JTAG driver. The interpreter processes and translates JTAG design files. The host side JTAG driver generates messages for the target side JTAG driver based on the translation. The host JTAG driver delivers the messages to a host network interface. The host network interface is connected via a network link to a target network interface. The target network interface is connected to the target side JTAG driver. The target side JTAG driver communicates with a target boundary scan chain. The target side JTAG driver and host side JTAG driver communicate over the network link. Network overhead is reduced by buffering messages until a message requiring a return of test data is ready for transmission.

A circuit is disclosed that includes a latch circuit and boundary scan cell circuitry. The latch circuit includes a slave latch and a master latch having a data output. The slave latch includes at least a first data input connected to the data output of the master latch, a second data input, and a control input that receives a control signal that controls latching of data present at the second data input. The boundary scan cell circuitry is connected to the second data input and to the control input of the slave latch so that the boundary scan cell circuitry can supply the control signal and data to the slave latch. In one embodiment, the boundary scan cell circuitry is IEEE1149.1-compliant and the circuit further includes either an output driver coupled to the data output of the slave latch or an input receiver coupled to a data input of the master latch.

A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.

A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a software tool during slice creation to create at least one slice connectivity file. During instance creation, a customer designs a custom chip using the software tool by selecting which structures are to be use on the slice. The slice connectivity file is then reused for the instance by reading the connectivity file to determine which structures in the file are used and not used based on the customer's selections. Thereafter, the slice is reconfigured to include dummy logic in unused structures, such that the boundary scan chain retains the same length and order.

A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary scan of targeted hardware using JTAG commands and architecture is described. The FPGA-based JTAG host controller is bussed directly into the FPGA core, bypassing the board's JTAG communication port.

In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary scan and other forms of testing), custom driver/receiver circuitry, etc. The pad ring in the programmable logic device, on the other hand, may be predetermined as part of the production of the programmable logic device. The generation may include removing the pad logic and other pad-related circuitry from one or more design files that represent the integrated circuit, as well as mapping the input, output, and input/output signals of the integrated circuit to the available programmable logic device pads.

A semiconductor device includes a JTAG boundary scan compliant testing architecture built into the semiconductor device, where the semiconductor device has a number of input points and output points. The JTAG boundary scan compliant testing architecture includes a TAP controller capable of receiving input test data, a test mode-select, and a test clock. In one embodiment, a full JTAG disable interface is utilized whereby the JTAG boundary scan compliant testing architecture allows an authorized user to prevent an unauthorized user from storing data into or reading data from input boundary scan registers and from reading data from output boundary scan registers. In another embodiment, a partial JTAG disable interface is utilized whereby an authorized user can prevent an unauthorized user from storing data into a pre-designated input boundary scan register, or from reading data from a pre-designated output boundary scan register.

The invention discloses a fault injection system for an embedded spaceborne computer and an injection method thereof, which are mainly used for software evaluation of the operation system of the spaceborne computer. The fault injection system for the embedded spaceborne computer comprises a Digital Signal Processor (DSP), a Random Access Memory (RAM), a FLASH, a Joint Test Action Group (JTAG) controller, and one or more Field Programmable Gate Arrays (FPGAs) (one of which is a fault injection FPGA) and an interface circuit, wherein the DSP processor and the fault injection FPGA are provided with boundary scanning units; the Test Compatibility Kit (TCK) and the Time-Multiplexed Switching (TMS) signal terminals of a chip are connected in parallel; the Total Domestic Output (TDO) signal terminal of a front-stage apparatus and the Transport Driver Interface (TDI) signal terminal of a rear-stage apparatus are connected in series to form a daisy chain. The device is simple and is capable ofshortening evaluation time and reducing evaluation cost; a signal level is directly controlled in the computer without special external instruments; signals needing to control influence can be flexibly selected to have a relatively large fault coverage rate; therefore, the reliability and the fault-tolerant capability of the embedded spaceborne computer can be more comprehensively verified.

The invention provides a boundary scanning system and a method based on high-performance computing communication framework. The system comprises a main master board, a business single board, a backboard, and a senior interlayer card module, further a JTAG controller equipped on the main master board for transmitting control information to business single board; a JTAG Grade I bridge equipped on the business single board for connecting JTAG equipment on the business single board; and a JTAG Grade II bridge equipped on the senior interlayer card module for connecting JTAG equipment on the senior interlayer card module.

A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells associated with pins of the circuit, the cell having a single-bit shift register element and an associated update latch, comprises a logic circuit for controlling the logic state of an associated pin, analog switches connecting the associated pin to analog test buses, and logic circuitry for selectively configuring the cell in a parametric test mode in which the cell shift register element controls the analog switches, and in a digital test mode in which the cell shift register element controls the logic state of the associated pin.

The invention relates to a method for designing testability of a chip, which comprises the steps: (1) insertion of a built-in self test circuit of a memory; (2) insertion of a boundary scan circuit; (3) integration of a testability circuit; (4) insertion of a scan chain circuit; and (5) generation of automatic test generated vectors. In order to solve the technical problems that in the traditional chip design process, a set of complete and systematical method in test methods aiming at different test objects is not available, tools such as a DFT (diagnostic function test) tool, a logic synthesis tool, a circuit simulation tool and the like are not joined and the design program is complicated, the invention provides the process guarantee for automation of the DFT design and complete and systematical correctness of the DFT design.