326 results about "Boundary scan" patented technology

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I / O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and / or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

The invention provides a method and circuitry to save power in a synchronous logic ASIC with low overhead. The scan chain(s) and boundary scan mechanism of the synchronous logic ASIC are used and modified for shifting out current states of internal memory devices of the synchronous logic ASIC to an external memory and for retaining the power-off blocks' primary output values to the memory devices of the boundary scan circuit, so the proposed gated power method is efficient and low overhead in the synchronous, flop-based, logic circuit design.

A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a software tool during slice creation to create at least one slice connectivity file. During instance creation, a customer designs a custom chip using the software tool by selecting which structures are to be use on the slice. The slice connectivity file is then reused for the instance by reading the connectivity file to determine which structures in the file are used and not used based on the customer's selections. Thereafter, the slice is reconfigured to include dummy logic in unused structures, such that the boundary scan chain retains the same length and order.

In accordance with at least one embodiment, a method, apparatus, and article of manufacture are provided for configuring a virtual boundary register in a programmable logic device (PLD), transmitting a first user-definable-command operation code (opcode) to the PLD to effect programming of a memory device coupled to the PLD, and preferably transmitting a second user-definable-command opcode to the PLD, the second user-definable-command opcode causing the physical boundary scan circuitry to load the virtual boundary register. The foregoing is preferably achieved in accordance with a boundary scan standard (e.g., Institute of Electrical and Electronics Engineers, Inc. (IEEE) 1149.1, dated 2001).

A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells associated with pins of the circuit, the cell having a single-bit shift register element and an associated update latch, comprises a logic circuit for controlling the logic state of an associated pin, analog switches connecting the associated pin to analog test buses, and logic circuitry for selectively configuring the cell in a parametric test mode in which the cell shift register element controls the analog switches, and in a digital test mode in which the cell shift register element controls the logic state of the associated pin.

A chain of boundary scan registers is configured to use a two-phase clock signal to avoid data timing race conditions. The two-phase clock signal is generated according to a two-phase clock generator, which includes two self-timed clock pulse generators for each boundary scan register. The two-phase clock generator locally generates a self-timed clock pulse at the rising edge of a clock signal, which triggers a first stage of the boundary scan register. The two-phase clock generator also generates a self-timed clock pulse at the falling edge of the input clock signal, which triggers a second stage of the boundary scan register. The two-phase clock controlled boundary scan register includes two latches, each latch is triggered by one of the self-timed clock pulse generated locally from the rising and falling edge of the input clock signal.

Embodiments of the present invention are directed to performing boundary scanning without using a pin which is exclusively dedicated for that purpose. The boundary scan can be performed by an integrated circuit by utilizing a pin which has an alternative use during ordinary operation of the integrated circuit and the device. This pin can be connected to an analog circuit configured to sense capacitance outside of the pin. The analog circuit may also have an alternative function in normal operation of the device. During a testing mode, the analog circuit can sense a stray capacitance present at the pin. The sensed capacitance can be compared to one or more stored expected capacitance values to determine an interconnection state of the system.

A mask programmable IC is provided that includes dedicated boundary scan logic in the I / O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I / O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I / O pad, each cell alone being capable of providing the boundary scan functions associated with one I / O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. These interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.