447 results about "Testability" patented technology

A method of fabricating a semiconductor package comprising the step of providing a leadframe strip which defines a strip plane and a multiplicity of leadframes. Each of the leadframes includes an outer frame defining a central opening and a die pad disposed within the central opening. Each leadframe further includes a plurality of leads which are attached to the outer frame and extend toward the die pad in spaced relation to each other. The outer frames are integrally connected to each other and collectively define connecting bars which extend in multiple rows and columns and define saw streets. Semiconductor dies are attached to respective ones of the die pads, with the semiconductor dies being mechanically and electrically connected to the leads of respective ones of the leadframes. Thereafter, an encapsulant material is applied to the leadframe strip to form at least one mold cap which at least partially encapsulates the leadframes, the semiconductor dies, and the conductive wires. The leadframe strip and the mold cap collectively define a package strip. Isolation cuts are formed through the package strip along at least some of the saw streets to effectively electrically isolate the leadframes from each other.

The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.

An error correction code system for a memory for improving performance and testability. The parity columns of the memory array can be positioned centrally within the array to minimize routing distance to ECC logic circuitry. The parity columns can be grouped together or distributed throughout the array to optimize performance. A multiplexor circuit can be included for selectively coupling only the parity bits stored in the parity memory array to I/O circuitry. Therefore, the parity columns can be directly tested, and testing of the ECC logic circuitry is facilitated.

Apparatus enabling modular implementation of active optical cable (AOC) with multiple integrated functions including: integration of different types of data on the AOC via media conversion; distribution of electrical power over the AOC; electrical multiplexing data channels for optical fibers; integration of voltage regulators enabling AOC operation at different supply voltages; integration of voltage regulators to provide stable, low noise power source; ruggedized, blind-mateable electrical connectors; integration of electronics and optoelectronics inside a connector backshell; implementation of health monitoring and test channel enabling monitoring, test, and control of both ends of the AOC and monitoring and control of upstream systems and components; and enabling a form, fit, function replacement of existing electrical cables to improve SWaP, electromagnetic interference resiliency, length-bandwidth product, electromagnetic pulse resistance, signal integrity, system reliability, testability and maintenance. AOCs are customized for different connectors, pin-outs, electrical data combinations, power distribution and power supplies with minimal redesign/requalification.

A graphical user interface (GUI) provides a design engineer the capability of automatically inserting scan logic and test logic into a design. The graphical user interface includes a scan insertion option for a design engineer to invoke a scan insertion tool to check the design for testability. The graphical user interface also permits the design engineer to invoke a test generation tool such as an automatic test pattern generator (ATPG) tool to check the design for fault coverage. The graphical user interface, which can serve as a front end for a design framework, enables a design engineer to efficiently increase testability while still in a design phase.

A system, method and computer program product is disclosed for evaluating system architectures from a long term sustainability perspective, sustainability in the presence of rapidly evolving information and networking technology, rapidly evolving customer requirements and expectations, and rapidly evolving standards and protocols. The multi-attribute architecture evaluation method can include specific architectural characteristics. At the top level the present invention can include four architectural characteristics or attributes: modularity, commonality, standards-based, and reliability/maintainability/testability (RMT). The attributes can be further classified into sub-attributes and metrics to facilitate the comparative evaluation of candidate system architectures. In an exemplary embodiment of the present invention a decision support system, method and CPP for evaluating supportability of alternative system architecture designs is disclosed including: an analytic hierarchy process (AHP) model including a plurality of attributes, wherein the plurality of attributes includes: a commonality attribute; a modularity sub-attribute; a standards based sub-attribute; and a RMT sub-attribute. The present invention in an exemplary implementation can be embedded within a commercially available AHP shell, to facilitate adaptation to specific domains.

The invention discloses a method for testing realtime service transmission performance of the WiMAX network, belongs to the wireless broadband access field. In the method, a mobile terminal establishes RTSP media session connection with a streaming media server; the streaming media server receives a session request according to the mobile terminal, determins corresponding coding speed, encapsulates realtime UDP messages, then sends to the mobile terminal through the WiMAX network, the mobile terminal analyzes received UDP messages; when the network connection is time-out, the mobile terminal stops the RTSP media session connection with the streaming media server, calculates performance indexes of the transmission rate, the packet loss rate, time delay and the time delay jitter according to the analysis result of the UDP messages. The invention also discoses a terminal for testing realtime service transmission performance of the WiMAX network. The invention acquires performance indexes such as the transmission rate, the packet loss rate, time delay and the time delay jitter, etc., under different Qos allocation, improves testability and analyzability.

There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

A method and apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules. Such systems provide lower cost, improved testability/repairability and greater density than conventional modular packaging techniques, such as printed circuit boards and multi-chip modules. The non-conductive interconnection technique of the invention can be applied to all levels in the packaging hierarchy, from bare semiconductor dies to complete functional sub-units. Numerous exemplary systems and applications are described.

The invention relates to a design method of an integrated circuit and a hardware trojan detection method. The design method comprises the following steps of acquiring a code of a register transfer level of an initial integrated circuit design; confirming a node position embedded by a potential hardware Trojan in the initial integrated circuit design according to the code; simulating the initial integrated circuit design to obtain a simulating circuit; computing the logic value probability of an interconnection line of the node position in the simulating circuit, and carrying out insertion design of testability circuits on the interconnection line of the node position according to the logic value probability; sequentially connecting the testability circuits in the simulating circuit to form a scan chain, and acquiring a new integrated circuit design according to the simulating circuit with the scan chain, wherein the scan chain is used for detecting the position of the hardware trojan of the integrated circuit according to the input test signals and the output results. According to the integrated circuit designed by the scheme of the invention, the position of the hardware trojan can be found, and the cost is reduced.

A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and which improves testability of the semiconductor storage device. A plural number of holding circuits (103) are provided holding write data for memory cells of a memory cell array (101-1). The write data from the holding circuits (103) are written in the memory cells of the selected address. A plural number of comparators (CCMPN) are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted value or the inverted value of the write data held by the holding circuits (103) is output as the write data to the memory cells and as expectation data to the comparators (CCMPN) depending on the value of the inversion control signal (DIM). A decision circuit (104) is provided which outputs an error flag based on a coincidence detection signal (MATCH0) coupled to the plural comparators.

A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.

A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop. In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes.

The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack.

The invention relates to a method collaborating and optimizing the test data and the power consumption of testing large scale integrated circuits. The method relates to the technical field of the large scale integrated circuits and is proposed to resolve the problem that in the prior art of SOC test, no method is available to effectively reduce the test data and the power consumption of test at the same time. The method has the following steps: the compatibility of scanning units of the circuit is analyzed and accordingly the scanning units are classified into three categories; each category of scanning units are connected respectively, and a scanning chain with copying mechanism is built; a set of test vector is adjusted according to the new scanning chain structure; the test set is compressed by the method based on the compression of repeated data and a compressed test set T_E is acquired. When in the testing process, the compressed data is fully recovered by a decompression circuit to be tested. The invention discloses a design method for the testability of integrated circuits, and reduces the power consumption of circuits in the testing process, thus ensuring the reliability and testability; furthermore, the invention can effectively reduce the quantity of test data, shorten the test process, and lessen the number of ATE channels.

The invention relates to an accident detection system and method of SoC System on a chip, which comprises the following parts: strong detection circuit for complete integration chip; detection invitation mechanism whose circuit connects together with serial detection buses; parallel detection bus; IP (Intellectual Property) seed rim packaging chain circuit unit; clock controlling unit and IP seed selection decoding unit. The invitation detection mechanism consists of IP seed independent invitation detection mechanism and IP accident invitation detection mechanism between seeds. This invention adapts each present IP (DFT Design for Testability) method to detect circuit by system layer and IP seeds, which improves system accident percentage of coverage on the integration chip.

The invention relates to a method for designing testability of a chip, which comprises the steps: (1) insertion of a built-in self test circuit of a memory; (2) insertion of a boundary scan circuit; (3) integration of a testability circuit; (4) insertion of a scan chain circuit; and (5) generation of automatic test generated vectors. In order to solve the technical problems that in the traditional chip design process, a set of complete and systematical method in test methods aiming at different test objects is not available, tools such as a DFT (diagnostic function test) tool, a logic synthesis tool, a circuit simulation tool and the like are not joined and the design program is complicated, the invention provides the process guarantee for automation of the DFT design and complete and systematical correctness of the DFT design.

A semiconductor integrated circuit which is provided with a shift scan path incorporated in each function module and a testing I/O terminal connected to a shift scan path and provided separately from a normal-operation-use I/O terminal, and which comprises, all formed on one semiconductor chip, a bus interface circuit for connecting normal-operation-use I/O terminals of a plurality of function modules to a bus, an external interface switching circuit which switches between the bus-side I/O terminal of the bus interface circuit and the testing I/O terminal of each function module for connection to an external terminal and an interface control circuit for switch-controlling the external interface switching circuit.

The invention discloses an optimization method of capturing power consumption in a scan test. The optimization method of capturing power consumption in the scan test comprises the following steps: generating a netlist with a scan chain; grouping gating control clock units; designing a power constrain unit; combining with the generated netlist with the scan chain, conducting chip layout design which comprises a floorpan, a layout, a clock tree sythesis and wiring; reading a gate-level netlist with a scan structure, a process library, a timing sequence constrain file and a test protocol into an automatic test vector generating tool after the chip layout design is completed, conducting testability design rule checking, and generating a test vector; and conducting gate-level simulation to the test vector generated. By means of the optimization method of capturing the power consumption in the scan test, the capturing power consumption in a test process can be reduced significantly, the reduction of coverage or the sharp increase of the quantity of test vectors is not generated, changing of a test design process is needless, and realization is easy.

The invention relates to a system maintenance time distribution method based on operation decomposition, which comprises the following steps: 1. analyzing tasks, the step of analyzing the tasks comprises distribution request analysis, distribution object analysis, maintenance activity and influence factor analysis, wherein the distribution object analysis is mainly used for determining distributive system levels, functions and structural levels of all components of a device, and a product decomposed into the needed level by the system, namely, a replaceable unit, and mapping systemic functions and structural level diagrams; and the number of the levels is determined by complexity level of the device; 2. obtaining data, obtaining existing data of a distribution object required to be analyzed, namely, data of a similar product, fault frequency data, reachability data, testability data and the like; 3. selecting a distribution method, selecting high-level distribution or low-level distribution according to the stage of product design and the product level; 4. distributing indexes, distributing maintainability indexes of the given product to product units at all levels according to the selected method; 5. analyzing a result, judging whether a distribution result is in line with requirements and is feasible.

The present invention discloses a universal system for electronic equipment testability validation and evaluation and a testing method, relating to the technical field of the monitoring device or method of electronic equipment. A master control subsystem is used for generating a fault signal and injecting the fault signal into a fault injection subsystem. A state monitoring sub system is used for collecting corresponding fault signal information according to a fault signal monitoring point set by a user, transmitting the information to the master control subsystem in real time and carrying out displaying. The fault injection subsystem is used for generating a corresponding fault signal according to the control command issued by the master control subsystem, coupling and transferring the generated fault signal and inputting the signal to tested electronic equipment through a universal adapter. According to the system, enough failure modes, testing resources and flexible software and hardware configurations are provided, and the various testability validation and evaluation tests of actual electronic equipment can be accurately supported.

The invention relates to the technical field of electronics and discloses a DC-DC power supply device, a voltage regulation method and network equipment in order to improve the testability of circuits. In the invention, at least one regulation module and a control module are arranged in the DC-DC power supply device, wherein the control module controls the conduction states of upper and lower switch tubes in a resistor array in the regulation module so as to regulate the offset of an output voltage to control the size of the output voltage. Thus, the synchronous regulation of one or more DC-DC switch power supply modules can be realized without manual box opening and power-interrupting operation and the precision regulation of the output voltages of the DC-DCs switch power supply modules is realized without a large amount of circuit hardware regulation and change, so that the testability of the circuit and operation smoothness of the whole circuit test process are improved effectivelyand the product test and examination work is very convenient. The invention also discloses the power supply method and the network equipment.