25 results about "Design for testing" patented technology

The invention relates to the technical field of probe testing, in particular to a PCB flying probe test path optimization method based on electrical characteristics, which comprises the following steps: calculating accessibility scores of test points according to the distribution of board surface test points and elements to determine risk types of the test points; determining a risk area grade corresponding to the grid unit according to the accessibility score in combination with the potential shadow area; optimizing the test path of the probe according to the risk area grade corresponding to the grid unit, and adjusting the initial moving speed of the test path of the probe in different grid units; for the same moving time sequence of different probe groups, determining overlapped grids according to the initial probe angles and the test paths corresponding to the probes, and determining whether there is a collision risk between the probes in combination with the initial moving speeds of the probes in different grid units; and when a collision risk exists between the probes, corresponding adjustment measures are taken according to the number of the overlapped grids. According to the invention, the test path is optimized in combination with multi-dimensional design based on the electrical characteristics and testability of the board.

A circuit for design-for-test (DFT)-mixing and internal clock pulse generation in test and functional modes includes a tristate inverter; a reset circuitry; and a clamp circuitry, where such clamp circuitry is configured for design-for-test (DFT)-mixing. A method for design-for-test DFT-mixing includes: in a test mode, providing a DFT information signal to a circuit; in response to receiving a clock signal at a clamp circuitry, retaining the DFT information signal at the clamp circuitry; and in response to a transition of the clock signal, deactivating the clamp circuitry and generating an internal clock pulse. A method for DFT-mixing includes: in a functional mode, providing, from a tristate inverter, a CTR signal on a critical path of a circuit; in response to an external clock signal, receiving at a logic circuitry coupled to the critical path, at least the CTR signal; and generating, by a first stage of the logic circuitry, an internal clock pulse.

The invention discloses a three-dimensional packaging chip system with a built-in interconnection test function and a detection method thereof, and the system comprises a packaging semiconductor main body which is internally provided with a plurality of wiring layers, a testability design (DFT) circuit which is integrated in a chip, and an internal multi-channel selection switch network which is controlled by the DFT circuit and is arranged on each wiring layer. And at least two detection pins / pads which are arranged outside the package and have a small number and increased pin spacing. According to the method, the DFT circuit is used for controlling switching of the switching network, different internal interconnection paths are multiplexed to the detection point in a time division mode for electrical measurement, and accurate positioning of fault nodes is achieved by analyzing multiple sets of measurement results. According to the method, the problem that the needle card is difficult to test due to warping of high-density packaging is effectively solved, hierarchical and nodal accurate diagnosis of internal interconnection faults of three-dimensional packaging is realized for the first time, the test cost and complexity are remarkably reduced, and a hardware basis is provided for online function repair.

The embodiment of the invention discloses a packaged chip failure detection method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuit packaging, and is convenient for analyzing the influence of a packaging process on the electrical performance of a circuit. The method comprises the steps of designing a test path based on testability, and detecting a packaging interface of an independent chip before packaging so as to determine whether a transmitting end circuit, a receiving end circuit and a non-working state circuit of the chip before packaging are invalid or not; designing a test path based on testability, and detecting a packaging interface of the packaged interconnected chips so as to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the packaged chips fail or not; and comparing the chip detection result before packaging with the chip detection result after packaging, positioning a failure position and evaluating the influence of packaging on the circuit. The method and the device are suitable for the scene of failure detection of the packaged chip.

The invention relates to the technical field of integrated circuit testability design, in particular to a testability design method and circuit based on high-speed digital signal processing, and the method comprises the steps: obtaining a to-be-tested circuit, and analyzing a test demand; the method comprises the following steps: setting a circuit in a working state, and generating a control signal and a control cycle signal by adopting a BIST CONNTROLLER; adopting a PRBS generator to receive the control signal and generate a test random number, and inputting the test random number into the circuit to be tested to obtain test data; receiving the control cycle signal by adopting an MISR module, and compressing the test data to obtain a simulation signature value; the uniqueness of the simulation signature value is judged; judging whether the test coverage rate meets test requirements or not; outputting a simulation signature value; the invention discloses a testability design method and circuit based on high-speed digital signal processing, and the method and circuit are used for judging whether a to-be-tested circuit has defects or not by adopting the synchronous design of an asynchronous clock signal.

Certain aspects of the present disclosure provide a method to define at least one register transfer language (RTL) level parameter for a design for test (DFT) wrapper module including at least one DFT sub-module including an RTL logic. A number of instances of the at least one DFT sub-module may be based on a value of the at least one RTL level parameter. The at least one DFT sub-module may be used for testing a system-on-a-chip (SoC) chip.

The invention discloses a chip testability design method, electronic equipment and a computer readable storage medium, and relates to the technical field of integrated circuit design and testing.The chip testability design method comprises the steps that multiple test items of a chip are obtained, the multiple test items at least comprise a first test item and a second test item, and the first test item and the second test item are matched with each other; the first test item is a test item for a first module group of the chip, the second test item is a test item for a second module group of the chip, and the first module group is different from the second module group; test parameters of the first test item are configured through the JTAG port, and a first main body operation stage corresponding to the first test item is entered; and during the running period of the first main body running stage, testing parameters of the second testing item are configured through the JTAG port, and a second main body running stage corresponding to the second testing item is entered. The test time can be shortened, and the test cost can be reduced.

The application discloses a testable design circuit of SRAM, and a write path circuit detection mode of a fault diagnosis logic control module, wherein the write path circuit is in a conducting state, a write data bit selector is in a selection state, a read data bit selector is in a non-selection state, a read path circuit is in a conducting state, and a storage unit is in a selection state; in a read path circuit detection mode, the write path circuit is in a non-conducting state, the write data bit selector is in the selection state, the read data bit selector is in the non-selection state, the read path circuit is in the conducting state, and the storage unit is in a non-selection state, and a bit line signal end is connected with a test signal output by a signal generation circuit. The application can improve the judgment ability and efficiency of functional failure faults existing in the write path circuit and the read path circuit in the fault diagnosis process. The application further discloses a read-write path decoupling circuit of SRAM, which can realize double-port output by using a single-port storage unit.

The invention relates to the technical field of integrated circuit testability design, in particular to a testability design method based on a multi-frequency-division clock high-speed digital processor, which comprises the following steps of: acquiring a circuit to be tested, carrying out preprocessing and DFT (Discrete Fourier Transform) design on the circuit to be tested, and introducing an OCC module based on a three-way clock synchronization circuit, and carrying out testability design on the block-level circuit and the top-level circuit in sequence. The invention provides a testability design method combining SCAN CHAIN and LBIST, an EDT compression mechanism is adopted, a three-way clock synchronization circuit is used, high-coverage-rate fault testing is carried out on a chip based on a test vector generated by ATPG, under the condition that resources are limited, the test efficiency is improved, and the test efficiency is improved. According to the invention, the fault diagnosis and test of the multi-working-mode, multi-frequency-division clock and clock multi-phase high-speed digital signal processor under the asynchronous clock are carried out, the test cost is reduced, a reference is provided for the fault test of the high-speed digital signal processor, and the chip yield is improved.

Generating an integrated circuit (IC) includes receiving Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry of an integrated circuit (IC) design, and partitioning the DFT CODEC circuitry into two or more sub-blocks based on a number of scan chains within the IC design. Further, scan chains are assigned to each of the two or more sub-blocks based on locations of end points within the scan chains. A layout of the IC design is generated by placing the DFT CODEC circuitry within the IC design based the locations of end points within the scan chains and the assigned scan chains to each of the two or more sub-blocks.

The invention discloses a multi-core cascade EDT scanning test circuit and a test method, and relates to the field of integrated circuit test and testability design. In order to improve the multi-core chip test efficiency and reduce the test cost, the invention provides a cascaded EDT scanning test circuit which comprises a plurality of EDT compression interface modules which are sequentially connected in series, and each module wraps a core to be tested; the serial EDT control module is used for uniformly controlling test data decompression, signature compression, bypass and mask updating operation of each core; the EDT modules are in cascade connection through a data channel with a fixed bit width to form a cross-core scanning path. According to the scheme, the EDTs of the multiple to-be-tested cores with the same compressed data bit width and the scanning chains in the cores can be connected in series, the test operation mode is similar to the mode that the scanning chains are used for mounting the multiple to-be-tested cores without the EDTs in series, and the test operation mode is compatible with an existing JTAG interface time sequence. The scheme supports dynamic bypass and mask configuration, is simple in circuit, can be used as an independent test scheme, can also be embedded into an existing SSN test architecture to reduce the number of SSH nodes and configuration overhead, and is suitable for multi-IP core chip scanning test.

The invention discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that asynchronous logics have no time sequence relation and do not need time sequence check, selectors in OCC circuits fixedly select high-speed clock output paths, and a front-end selector is additionally arranged at the front end of each OCC circuit, so that the time sequence check is not needed. A path selection signal of a front-end selector is used for selectively inputting a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters an OCC circuit and then is output through a high-speed clock output path of an internal selector, and therefore, an asynchronous clock domain relationship is kept between clocks output by different OCCs; therefore, the cross-domain time sequence check between different clock domains is not triggered, the time consumption of time sequence convergence iteration performed by the rear end due to the cross-domain time sequence check is saved, and the overall development period of the chip is shortened.

The invention provides a test point collaborative iterative optimization method for testability design based on logic deep optimization, and belongs to the field of integrated circuit digital chip scan chain testing. The invention provides a test point optimization design method for solving the problem that the test coverage rate is too low when a circuit carries out automatic test vector generation. The core method comprises the following steps: screening an initial test point set from an original circuit through a Tesent tool, converting output test point information into a constraint file compatible with a DFTC tool, and dynamically adjusting a scan chain insertion strategy; and performing logic depth value traversal on the inserted test points, evaluating the test values of the inserted test points, and iteratively and optimally inserting the test points with low logic depth values and high signal activeness so as to optimize the test coverage rate. The method is mainly applied to testability design of a digital chip, test point selection and scan chain insertion are collaboratively optimized through an EDA tool, the test coverage rate is improved through test point logic depth, and hardware overhead is reduced.

The invention discloses a storage chip and a storage module. The memory chip comprises a one-time programmable circuit configured to burn and store data information; the testability design circuit is connected with the one-time programmable circuit, and the testability design circuit comprises a plurality of main control modules; wherein in response to the power-on broadcast of the storage chip, the one-time programmable circuit generates an address signal based on a clock signal, and addresses a corresponding main control module in the testability design circuit based on the address signal; the one-time programmable circuit registers data information to a corresponding main control module in the testability design circuit through a data transmission bus according to the rhythm of the clock signal; the data transmission bus comprises a plurality of data transmission lines, and the number of the data transmission lines is determined by the bit width of the data information and the number of address invalid bits which do not participate in address decoding in the address signal. According to the invention, line resources are saved, so that the performance of the memory chip is improved.

This invention provides a multi-chip system and a method for operating the multi-chip system. The multi-chip system includes a first chip and a second chip. The first chip and at least one second chip are disposed on a circuit layer. The first chip includes a first select pin and a first test circuit. The first select pin receives a first select signal. The first test circuit is coupled to the first select pin and includes multiple first input / output pins. Each second chip includes a second select pin and a second test circuit. The second select pin receives a second select signal. The second test circuit is coupled to the second select pin and includes multiple second input / output pins. The multiple first input / output pins are correspondingly connected to the multiple second input / output pins of each second chip and are connected to multiple common traces. The multi-chip system and the method for operating the multi-chip system of this invention can effectively save the number of solder balls and provide good design-for-test functionality.

The application discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that there is no timing relationship between asynchronous logics and timing checking is not needed, a selector inside an OCC circuit is fixed to select a high-speed clock output path, a front-end selector is added in front of each OCC circuit, and a path selection signal of the front-end selector is used to select a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters the OCC circuit and is output through the high-speed clock output path of the internal selector, so that the clocks output by different OCCs maintain an asynchronous clock domain relationship, so that cross-domain timing checking between different clock domains is not triggered, time consumption of timing convergence iteration performed at the back end due to the cross-domain timing checking is saved, and the overall development cycle of the chip is shortened.

The application relates to the technical field of probe testing, in particular to a PCB flying probe test path optimization method based on electrical characteristics, which comprises the following steps: determining the risk type of a test point according to the accessibility score of the test point and the distribution of the test point and elements, and determining the risk area grade corresponding to a grid unit according to the accessibility score and a potential shadow area; optimizing the test path of a probe according to the risk area grade corresponding to the grid unit, and adjusting the initial moving speed of the test path of the probe in different grid units; for the same moving timing sequence of different probe groups, determining overlapping grids according to the initial probe angle and the test path corresponding to the probe, and determining whether there is a collision risk between the probes according to the initial moving speed of the probes in different grid units; when there is a collision risk between the probes, corresponding adjustment measures are taken according to the number of overlapping grids. The application combines multidimensional optimization of a test path based on the electrical characteristics and testability design of a board.

The present application provides a multi-chip system and an operating method of the multi-chip system. The multi-chip system includes a first chip and at least one second chip. The first chip and the at least one second chip are disposed on a routing layer. The first chip includes a first selection pin, a first test circuit, and a plurality of first input / output pins. The first selection pin receives a first selection signal. The first test circuit is coupled to the first selection pin. Each second chip includes a second selection pin and a second test circuit. The second selection pin receives a second selection signal. The second test circuit is coupled to the second selection pin and includes a plurality of second test units. The plurality of first input / output pins are coupled to the plurality of second test units of each second chip through a plurality of die-to-die traces. The multi-chip system and the operating method of the multi-chip system of the present application can effectively save the number of solder balls and provide good testability design test functions.

The invention discloses a compression test system and method based on pin multiplexing, and relates to the technical field of testability design. The corresponding system comprises a plurality of chip passivation holes, a segment insertion byte unit, a test data register and a compression and decompression unit, wherein the compression and decompression unit is provided with an initial chip passivation hole and at least one standby chip passivation hole; the segment insertion byte unit and the test data register are arranged between the chip passivation hole and the compression and decompression unit, and are used for connecting the compression and decompression unit to a standby chip passivation hole configured by the compression and decompression unit under the condition that the initial chip passivation hole corresponding to the compression and decompression unit fails; or the compression and decompression unit is configured to a preset standby chip passivation hole or an initial chip passivation hole of the compression and decompression unit. According to the invention, the influence of the chip passivation trepanning performance on the internal logic test can be weakened.

A method for testing a first circuit design on an FPGA system, the first circuit design being compartmentalized into a plurality of interacting sub-designs. The method comprises a step in which a first sub-design of the first circuit design is mapped onto a first FPGA unit. Furthermore, a second sub-design of the first circuit design is mapped onto a second FPGA unit. In another step, a status variable for the first and second sub-design of the first circuit design are generated. The status variables are configured to indicate a readiness status of the corresponding sub-design for testing. In yet another step of the disclosed method, the status-variables of the first and second sub-design of the first circuit design are connected to a first superordinate FPGA unit each through a separate data channel.

The application provides a test vector verification method, system, device and readable storage medium. The method comprises the following steps: parsing a test vector file, for each test stage, storing the test data value sequence corresponding to each test signal in the test stage as a first data file respectively; combining the first data files into a second data file based on the execution order and the cycle number of each test stage in the target test vector file; constructing a test platform, reading the second data file, and driving the read data to the corresponding input pin of the design for testing netlist cycle by cycle; determining whether the response result of the output pin of the design for testing netlist is correct based on the corresponding test data value in the second data file. Compared with the prior art, the application can simulate the ATE test vector format file freely, cover the problems that cannot be verified by the conventional testbench, find the problems in advance before the ATE formal test, and accelerate the iteration of the ATE test program.

To provide a semiconductor device having a testing facilitation engineering interface.SOLUTION: A semiconductor device may be tested within a manufacturing environment as one of a die and a packaged die. A testing facilitation engineering interface includes a physical layer having a transmitter, a receiver and a common lane. The testing facilitation engineering interface includes a semiconductor device logic and a test port interface logic connectable by an interface. The test port interface logic may include a 1:N deserializer logic, a 1:N CLK frequency divider logic, and an N:1 serializer logic.SELECTED DRAWING: Figure 1

The invention provides a method for repairing a Hierarchical circuit based on netlist learning, and aims to solve the technical problems that in a traditional repairing scheme, logic resource consumption is high, a circuit hierarchical structure is prone to being damaged, and time delay power consumption is increased. The method comprises the steps that information of the Hierarchical circuit is obtained in a netlist learning mode, the connection state of a clock pin of a scanning unit is recognized according to the information, and therefore the Hierarchical circuit is repaired. According to the method, an optimal repair point is positioned by combining hierarchical structure analysis, a clock signal repair strategy based on minimum MUX module insertion is provided for a multi-clock scene, time delay accumulation and power consumption rise caused by excessive deployment of logic units in a deep module are avoided, and experimental results show that the method can significantly improve the test coverage rate and improve the test efficiency. And the occupation of logic resources for repairing the violation points is reduced, so that the technical bottleneck of repairing the multi-clock Hierarchical circuit is effectively broken through, and an efficient solution is provided for the testability design of a super-large-scale integrated circuit.

This invention discloses a circuit and testing method for testing analog circuits in 3D stacked chips, relating to the field of design for testability of 3D packaged chips. To meet the testing requirements of analog circuits in 3D stacked chips and achieve real-time monitoring of the voltage value of the analog signal under test, which changes relatively smoothly, this invention addresses the shortcomings of existing IEEE 1149.4 analog testing schemes, such as the susceptibility to interference during transmission within 3D packaged chips and the inability of low-resolution ADC schemes to quantitatively obtain voltage values. The invention proposes an analog circuit testing scheme based on Σ-Δ modulation. The testing circuit includes: a test control unit (TAP) conforming to the IEEE 1149 protocol, used to receive JTAG commands, select the node under test, and configure the sampling clock frequency and sampling number; an analog multiplexer (MUX) used to select the analog voltage signal of the specified node under test; a Σ-Δ modulator used to modulate the analog voltage into a 1-bit modulated square wave with a high-level ratio proportional to the voltage; a sampling control unit used to monitor the start command and generate a sampling clock, and control the discharge of the integrating capacitor of the Σ-Δ modulator; and a dedicated transmission channel for the modulated square wave across the entire chip. The analog signals of this invention are transmitted between stacked chips in the form of modulated square waves, providing interference immunity; the Σ-Δ modulation circuit has a simplified structure and low layout area overhead. The test circuit described conforms to the IEEE 1149 standard and is compatible with existing JTAG test equipment.

The invention discloses a signal processing method, a digital module, an analog module and a chip, and relates to the technical field of chip design and testing, the digital module of the chip is responsible for transmitting a test mode control signal and an original analog control signal, the analog module autonomously processes signal logic in a test mode, and the test mode control signal and the original analog control signal are transmitted to the digital module; and all registers on the digital side can be subjected to uplink scanning. Compared with the process that the number needs to manually screen the downlink register in the traditional scheme, the method has the advantages that the process that the number and simulation repeatedly confirm the downlink register is omitted, the communication cost is reduced, meanwhile, the problem that the register is missed to be tested due to downlink is avoided, and the coverage rate of testability design is increased.