4 results about "Design for testing" patented technology

Certain aspects of the present disclosure provide a method to define at least one register transfer language (RTL) level parameter for a design for test (DFT) wrapper module including at least one DFT sub-module including an RTL logic. A number of instances of the at least one DFT sub-module may be based on a value of the at least one RTL level parameter. The at least one DFT sub-module may be used for testing a system-on-a-chip (SoC) chip.

Generating an integrated circuit (IC) includes receiving Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry of an integrated circuit (IC) design, and partitioning the DFT CODEC circuitry into two or more sub-blocks based on a number of scan chains within the IC design. Further, scan chains are assigned to each of the two or more sub-blocks based on locations of end points within the scan chains. A layout of the IC design is generated by placing the DFT CODEC circuitry within the IC design based the locations of end points within the scan chains and the assigned scan chains to each of the two or more sub-blocks.

The application discloses an on-chip clock controller for testability design and an optimization method thereof, based on the thought that there is no timing relationship between asynchronous logics and timing checking is not needed, a selector inside an OCC circuit is fixed to select a high-speed clock output path, a front-end selector is added in front of each OCC circuit, and a path selection signal of the front-end selector is used to select a high-speed function clock signal or a low-speed test clock signal, so that the low-speed test clock signal enters the OCC circuit and is output through the high-speed clock output path of the internal selector, so that the clocks output by different OCCs maintain an asynchronous clock domain relationship, so that cross-domain timing checking between different clock domains is not triggered, time consumption of timing convergence iteration performed at the back end due to the cross-domain timing checking is saved, and the overall development cycle of the chip is shortened.

This invention discloses a circuit and testing method for testing analog circuits in 3D stacked chips, relating to the field of design for testability of 3D packaged chips. To meet the testing requirements of analog circuits in 3D stacked chips and achieve real-time monitoring of the voltage value of the analog signal under test, which changes relatively smoothly, this invention addresses the shortcomings of existing IEEE 1149.4 analog testing schemes, such as the susceptibility to interference during transmission within 3D packaged chips and the inability of low-resolution ADC schemes to quantitatively obtain voltage values. The invention proposes an analog circuit testing scheme based on Σ-Δ modulation. The testing circuit includes: a test control unit (TAP) conforming to the IEEE 1149 protocol, used to receive JTAG commands, select the node under test, and configure the sampling clock frequency and sampling number; an analog multiplexer (MUX) used to select the analog voltage signal of the specified node under test; a Σ-Δ modulator used to modulate the analog voltage into a 1-bit modulated square wave with a high-level ratio proportional to the voltage; a sampling control unit used to monitor the start command and generate a sampling clock, and control the discharge of the integrating capacitor of the Σ-Δ modulator; and a dedicated transmission channel for the modulated square wave across the entire chip. The analog signals of this invention are transmitted between stacked chips in the form of modulated square waves, providing interference immunity; the Σ-Δ modulation circuit has a simplified structure and low layout area overhead. The test circuit described conforms to the IEEE 1149 standard and is compatible with existing JTAG test equipment.