56 results about "Design for testing" patented technology

The invention relates to a method for designing testability of a chip, which comprises the steps: (1) insertion of a built-in self test circuit of a memory; (2) insertion of a boundary scan circuit; (3) integration of a testability circuit; (4) insertion of a scan chain circuit; and (5) generation of automatic test generated vectors. In order to solve the technical problems that in the traditional chip design process, a set of complete and systematical method in test methods aiming at different test objects is not available, tools such as a DFT (diagnostic function test) tool, a logic synthesis tool, a circuit simulation tool and the like are not joined and the design program is complicated, the invention provides the process guarantee for automation of the DFT design and complete and systematical correctness of the DFT design.

The invention discloses an optimization method of capturing power consumption in a scan test. The optimization method of capturing power consumption in the scan test comprises the following steps: generating a netlist with a scan chain; grouping gating control clock units; designing a power constrain unit; combining with the generated netlist with the scan chain, conducting chip layout design which comprises a floorpan, a layout, a clock tree sythesis and wiring; reading a gate-level netlist with a scan structure, a process library, a timing sequence constrain file and a test protocol into an automatic test vector generating tool after the chip layout design is completed, conducting testability design rule checking, and generating a test vector; and conducting gate-level simulation to the test vector generated. By means of the optimization method of capturing the power consumption in the scan test, the capturing power consumption in a test process can be reduced significantly, the reduction of coverage or the sharp increase of the quantity of test vectors is not generated, changing of a test design process is needless, and realization is easy.

A three dimensional (3D) stacked integrated circuit (IC) design-for-Testing (DfT) die-level wrapper boundary register having a bypass mode and design-level DfT delay recovery techniques are provided. Die wrappers that contain boundary registers at the interface between dies can be inserted into 3D ICs where the boundary registers include a gated scan flop with a bypass line passing the functional input to a through-silicon-via (TSV) in a manner avoiding the clocked stages of the gated scan flop during functional operation. A retiming process can be applied during design layout using a simulation/routing tool or standalone program to recover the additional delay added to the TSV paths by the DfT insertion. Retiming can be performed at both die and stack level, and in further embodiments, logic redistribution across adjacent dies of the stack can be performed for further delay optimization.

On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a “floated state” or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.

The invention relates to the field of testability design of an integrated-circuit technology and discloses a hardware-Trojan-resisting circuit design method based on activation probability analysis. The method mainly includes two parts: a first part: circuit design of a probability fuzziness unit and a second part: an insertion algorithm of the probability fuzziness unit. Targeting at characteristics of high elusiveness and high perniciousness of hardware Trojans, through analysis of a circuit node activation probability, the method selects an appropriate node to insert the probability fuzziness unit circuit so that an attacker is incapable of correctly judging a signal jumping probability of nodes in the circuit and inserts hardware Trojans only based on the circuit which undergoes probability fuzziness. Compared with the prior art, the hardware-Trojan-resisting circuit design method based on activation probability analysis is capable of strengthening the hardware Trojan resisting capability of a design circuit so that implanted hardware Trojans are incapable of achieving a specific objective designed by an attacker and are easily detectable in a test period.

An integrated circuit for performing a design for testability (DFT) scan test is provided. The integrated circuit includes at least one scan chain including a plurality of flip-flops, at least one interface scan chain including a plurality of flip-flops, a decompressor configured to be connected with an input terminal of the at least one interface scan chain and to decompress a first input signal and then transmit it to the at least one scan chain, a compressor configured to be connected with an output terminal of the at least one scan chain and to compress an output signal of the at least one scan chain, and at least one multiplexer configured to be connected with the decompressor and to selectively output an output signal of the decompressor or a second input signal in response to a control signal.

The invention discloses a DFT (Design for Testability) method for a double-edge trigger, which comprises the following steps of: on the basis of the existing VLSI (Very Large Scale Integrated) DFT method designed by internal scan, using a double-edge scanning trigger to replace a single-edge scanning trigger in the gate-level netlist file with a built scan chain; adding a test clock circuit; simulating a test vector generated through the scan chain circuit of the single-edge scanning trigger by the scan chain circuit comprising the double-edge scanning trigger; and using the simulated test vector to test the scan chain circuit by an ATE (Automatic Test Equipment) device. In this way, the VLSI DFT method disclosed by the invention can be suitable for the circuit comprising the double-edge trigger and the circuit comprising the single-edge trigger, and further, the method is suitable for popularizing the double-edge trigger in the VLSI design and finally multiplying data handling capacity and reducing half of the power consumption of the integrated circuit.

The invention discloses a register resetting method and device based on a scanning mode. The register resetting method comprises the following steps of: (1) constructing scan chains for all registers, respectively connecting data input ends and data output ends of the registers in the scan chains with a not gate, wherein the registers need to be reset to 1; and (2) continuously inputting a reset value 0 to the head of the scan chain. The register resetting device comprises a resetting control logic and a clock control logic which are respectively connected with each register; the register resetting device also comprises reset value converting units, the number of which is in one to one correspondence with the number of the registers needing to be reset to 1; each reset value converting unit comprises two not gates, wherein one of the not gates is connected with the data input end of the corresponding register in series, and the other not gate is connected with the data output end of the corresponding register in series. According to the register resetting method and device, the logic design can be simplified, the realization of resetting logic is transparent for testability design, and the workload of testability design can be reduced.

The invention provides a digital logic chip and a method of design for testing, wherein, the method includes setting corresponding logic devices between each scanning trigger in the digital logic chip and each observing pin, by the observing pin, signal of each scanning trigger can be observed in different time; after the signal pass over the logic device, the observing result is compared with the forecasted observing result so as to determine whether the digital logic chip is normal or not. The digital logic chip of the invention and the method of design for testing can realize the observation of circuit scanning test by adopting few pins.

A high frequency data transmission circuit including design for testability (DFT) features. An integrated circuit includes core control logic to provide a data signal and output drive logic including a local data latch and a transmitter. The data latch receives the data signal and provides true and complementary forms of the data signal to the transmitter over symmetrical signal paths. The transmitter provides an output signal to an external receiver.

The invention discloses a method and a system for designing the testability of a high-speed serial IO interface based on DLL clock recovery. The idea of the method is that a DLL clock recovery may provide a group of clocks with different phases, that a control and selection signal of a DLL testing control unit is set, that a sampling point testing clock can be generated by using the group of clocks with different phases, that data is sampled at different positions of a UI, that a built-in BERT generates a test vector in order to perform detection and statistic on bit errors and test a bit error rate bathtub curve, and that then a jitter separation program fits random jitter and deterministic jitter according to a gating point and bit error rate information and estimates bit error rate. The method is also capable of testing parameters such as jitter tolerance, and sensitivity or the like and provides a condition for system-level testability. An internal clock is used as a testing clock so that high testing precision is guaranteed. A built-in testing circuit has a small scale and is easy to produce. A testing process does not relate to the use of ATE. Therefore, cost of testing the high-speed serial IO with a desk-type instrument can be effectively reduced and testing time is shortened.

The invention discloses a synchronous data acquisition and communication circuit, which is realized through a programmable gate array and a matched circuit. The synchronous data acquisition and communication circuit is characterized in that the circuit uses an FPGA clock management module to generate a standard frequency, a differential synchronous signal is then obtained through frequency division, and the same differential synchronous signal source is adopted to trigger all synchronous units. In addition, the synchronous data acquisition and communication circuit introduces testability design and port expansion design through modular design. Compared with a former simple data acquisition or communication unit, acquisition and uploading of all data and complete functions can be realized. Due to the modular design idea, mutual influences can be reduced, diversity of module communication forms is enhanced, and due to the testability design idea, monitoring of working states of each module and the overall body can be enhanced, and the debugging efficiency and the troubleshooting efficiency are improved; and after all unused ports of the FPGA are expanded outwardly, unified management is realized, and function expansion is facilitated.

A system and a method for implementing design for testability is disclosed, in that the method includes the steps of inputting function description data for defining hardware functions represented in the form independent of architecture; recognizing register variables inferable by memory elements, which are contained in the function description data; simulating events induced by affixing random numbers to the register variables; extracting control signals contained in the function description data as extracted control signals; analyzing the results of the simulation with respect to the extracted control signals; inserting test points for control signals having low toggle rates among the extracted control signals; and executing logic synthesis on the control signals having low toggle rates including the test points.

The invention discloses an impact toughness detecting device and an impact toughness detecting method for an airport runway pavement structure, which relate to the technical field of airport runway pavement impact resistance detection. The impact toughness detecting device comprises a bottom plate, wherein a pushing hand for pushing the bottom plate is mounted on one side of the bottom plate, three side plates are mounted on the upper end of the bottom plate equidistantly, and the upper end of the bottom plate is provided with a servo motor at a position close to one side of the side plates. The impact toughness detecting device calculates impact forces to the airport runway pavement under different gravities by utilizing a gravitational potential energy formula can obtain different data for comparison under the conditions of different heights and gravities, adopts a double-row design for testing pavements the adjacent regions simultaneously, makes the operation more labor-saving by combining with the se of electromagnetic chucks, saves the trouble of manual calculation by comparing multiple sets of data and utilizing automatic calculation of the computer, is convenient to move, issuitable for testing multiple regions of the airport runway, saves time and labor, and is precise in detected data values.

The invention discloses a testability design structure for protecting an encryption chip from scanning attacks. The secure testability design structure of the encryption chip is introduced with key shielding logic, shift enabling logic and a secure scan controller based on the conventional scan design structure. If the encryption chip first enters the functional mode after power-on or reset, the key shielding logic allows the key to be loaded under the control of the security scan controller, while the shift enabling logic prevents the circuit from switching to the test mode, thereby avoidingthe leakage of the encrypted information. Conversely, if the encryption chip first enters the test mode after power-on or reset, the scan shift and the response capture can be performed normally underthe control of the security scan controller, while the key is isolated, thereby ensuring that the data removed from the scan chain is independent of the key. According to the secure testability design structure of encryption chip, by adding less hardware logic, all potential scan-based side channel attacks can be resisted while ensuring the circuit testability.

The present invention relates to an apparatus and a method of reading and writing an internal register file through an I2C interface. The apparatus comprises an I2C host, an I2C slave, a read and write operation unit, and a read and write enabling control unit. The I2C host sends a signal to the I2C slave and the read and write enabling control unit and reads data in the I2C slave. The I2C slave comprises a first I2C read and write register, a second I2C read and write register and an I2C read-only register that are respectively used for storing write ID and write data and read ID and read data. The read and write operation unit is used for performing read and write operations on the internal register file. The read and write enabling control unit is used for generating a read and write enabling signal according to the signal sent by the I2C host and setting 1 for controlling the read and write operation unit. When a write enabling signal is 1, the write operation is performed, and when a read enabling signal is 1, the read operation is performed and read data is fed back to the I2C read-only register. According to the apparatus and method, extra external interface overhead and internal stored circuit consumption are not increased, further, read and write are performed on the internal register file of the chip, so that the apparatus and method are significant for testable designs.

The invention relates to a FPGA/IP core logic code security rule detection method, which relates to the technical field of FPGA/IP core verification. The invention adds and realizes FPGA state machinedeadlock, internal three-state and other rule clauses in the self-defined safety rule detection clauses according to the combination of the designed self-defined safety rule detection clauses and theexisting commercial clauses, and improves the quality of FPGA code. Deleting rules that are not applicable to the design for testability of FPGA, electrical characteristics detection, and so on, effectively reduces the invalid warning rules.

The invention discloses a testability design structure for protecting an AES password chip from scanning attack in a boundary scanning design environment. According to the safe testability design structure, shift enable logic, scan chain mode switching reset logic and key isolation logic are introduced on the basis of a conventional boundary scan design structure. The shift enable logic is used for disabling a scanning shift operation in a functional mode; the scan chain mode switching reset logic enables the chip to execute a reset operation at first when switching from a function mode to a test mode, so that confidential information stored in the scan chain is protected; and the key isolation logic is used for isolating the encryption key in the test mode so as to prevent the attacker from obtaining the key information in the test mode. New input and output signals are not introduced, only little hardware expenditure is needed, the chip can be automatically protected, and all potential side channel attacks based on scanning can be resisted on the premise that the testability of the circuit is not damaged.

The invention relates to a testable design structure based on scanning confusing and used for protecting an encryption chip against scanning attacks. Based on a conventional scanning design structure,a scanning password register and an associated logic are introduced into a secure testable design structure, and it is required that test passwords are firstly loaded from a chip input port during testing. Chip testing can be performed normally only after correct test passwords are loaded. If an attacker does not understand a correct test procedure and does not have the correct test passwords, the attacker cannot load the correct test passwords through the specific input port within the specified time, and therefore no value can be swept for a scanning chain under the 1-2-128 probability, thereal state of the scanning chain cannot be observed from the output end, and non-intrusive attacks based on scanning are virtually impossible. On the premises that the circuit performance and the testing quality are not influenced and the testing time is not added, existing non-intrusive attacks based on scanning can be resisted.

The invention discloses a tooling fixture for a vibration test bench, which belongs to the technical field of tooling design for testing and is suitable for clamping and fixing cables, boxes and cylindrical electrical components when performing vibration tests. It is composed of cable vibration tooling, box type and cylindrical type vibration tooling. The tooling fixture for the vibration test bench of the present invention has the advantages of simple structure, good manufacturability, flexible clamping and strong versatility, can clamp various test pieces at one time, and is economical and time-saving.

Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.