Method and apparatus for securing digital information on an integrated circuit during test operating modes

Abstract

The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and / or permanent secrets stored in ROM and / or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] [0002] This patent application is related to the concurrent application "Attorney Docket No. 00100.07.0125, Method and Apparatus for Securing Digital Information on Integrated Circuit Read-Only Memory During Test Mode of Operation," both assigned to ATI Technology ULC. technical field [0003] The present invention generally relates to integrated circuits (ICs) and various modes of operation of integrated circuits, such as test modes including design for testability (DFT) modes, and further relates to encryption keys, cryptographic and other information, more particularly, methods and apparatus to avoid accessing the encryption keys, passwords and other information by operating the IC in DFT or similar test mode. Background technique [0004] Securing digital content and other information required for the operation of electronic devices often resorts to encryption keys and passwords stored in various locations on integrated...

AI Technical Summary

Problems solved by technology

However, this method has several disadvantages

First, by excluding registers, DFT test coverage will be reduced and overall IC yield will be reduced

Second, it is error-prone because the designer is required to confirm and manually remove the "secret-related" register from the DFT program, and it may be difficult or even impossible to accurately confirm the specific register that is confidential

Third, the method assumes that only the registers contain the secret and that the memory does not

This method also has the disadvantage that it requires a special DFT algorithm, which is not supported by industry standard computer-aided design (CAD) tools

The second disadvantage of this method is that its dependencies are confusing, but it may be challenged by determined hackers through reverse-engineering.

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