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Encryption chip safety testing method based on scanning confusing

A chip and security technology, which is applied in the field of security test structure, can solve the problem of not finding the patent invention of encryption chip security test method, and achieve the effect of high security performance, low area cost, and small area cost

Inactive Publication Date: 2019-04-16
CHANGSHA UNIVERSITY OF SCIENCE AND TECHNOLOGY
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Among the existing patents, no patented invention similar to the encryption chip security testing method based on scanning confusion was found

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  • Encryption chip safety testing method based on scanning confusing
  • Encryption chip safety testing method based on scanning confusing

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Embodiment Construction

[0017] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0018] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0019] like figure 1 As shown, the security scanning scheme of the present invention can be added a shift register (R1), a 2-bit counter, a D flip-flop (D1) and a small number of logic gates (G1~G5) on the basis of the conventional scanning structure. to fulfill. For block-based encryption algorithms (such as AES encryption algorithm), its hardware implementation includes at least 128-bit plaintext input. When the chip enters the test mode for the first time after power-on or reset, th...

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Abstract

The invention relates to a testable design structure based on scanning confusing and used for protecting an encryption chip against scanning attacks. Based on a conventional scanning design structure,a scanning password register and an associated logic are introduced into a secure testable design structure, and it is required that test passwords are firstly loaded from a chip input port during testing. Chip testing can be performed normally only after correct test passwords are loaded. If an attacker does not understand a correct test procedure and does not have the correct test passwords, the attacker cannot load the correct test passwords through the specific input port within the specified time, and therefore no value can be swept for a scanning chain under the 1-2-128 probability, thereal state of the scanning chain cannot be observed from the output end, and non-intrusive attacks based on scanning are virtually impossible. On the premises that the circuit performance and the testing quality are not influenced and the testing time is not added, existing non-intrusive attacks based on scanning can be resisted.

Description

technical field [0001] The invention belongs to the field of hardware safety, and more specifically relates to a safety test structure for protecting an encryption chip from scanning attacks. Background technique [0002] With the development of information and digital society, information security and confidentiality have become more and more important, and encryption algorithms have been widely used. Regardless of high-end security processors or low-end smart cards, in order to improve data throughput, encryption algorithms are usually implemented using hardware modules. Cryptographic algorithms have zero tolerance for errors, so cryptographic hardware needs to be rigorously tested. [0003] Scan design is a widely used testability design technology for integrated circuits. It enhances the testability of circuits by directly controlling and observing the state of internal flip-flops, and converts the test problems of sequential circuits into test problems of combinational...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318544G01R31/318586G01R31/318588
Inventor 王伟征王威蔡烁
Owner CHANGSHA UNIVERSITY OF SCIENCE AND TECHNOLOGY
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