34results about How to "Small area overhead" patented technology

The invention discloses an iterative computation matrix inversion method and system based on Cholesky decomposition, and relates to the technical field of DSP system optimization, and the method comprises the steps: obtaining a target source matrix; based on Cholesky decomposition, performing first iteration processing on the target source matrix to generate an upper triangular matrix; performing second iteration processing on the upper triangular matrix to generate an inverse matrix of the upper triangular matrix; performing conjugate transpose processing on the inverse matrix of the upper triangular matrix to generate a lower triangular matrix; wherein the lower triangular matrix is stored in the form of array storage; converting the storage mode of the inverse matrix of the upper triangular matrix into a sequential storage mode; and performing matrix multiplication processing on the inverse matrix of the upper triangular matrix and the lower triangular matrix to generate an inverse matrix of the target source matrix. According to the method, accumulative summation is replaced by iteration, complex multiplication and addition optimization calculation is adopted, multi-parallelism operation and parallelization processing zero padding operation are supported, a general matrix multiplication module can be adapted, and calculation time and area overhead are reduced.

The invention relates to the technical field of convolutional neural networks, and discloses a data processing method, device and chip based on a sensing, storage and calculation integrated framework, the method is used for processing convolution calculation of input matrixes [A1, A2,..., AM] of M * N input data, the size of a convolution kernel W is k, and the step length is s, the method comprises the following cycle steps: constructing an input sub-matrix Yi, forming a recombined convolution kernel Wi, and constructing the input sub-matrix Yi; and performing convolution calculation on Yi and Wi, and judging whether circulation is completed or not. According to the method, the device and the chip disclosed by the invention, the number of analog registers required by convolution operation in the sensing, storing and computing integrated chip can be effectively reduced through circulating control on input and weight, the area, the cost and the power consumption of the sensing, storing and computing integrated chip are greatly reduced, and the computing speed is improved.

The present invention relates to a pulse latch unit structure, comprising a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube and a gate control unit DUC, and realizing a latching function of an input signal. The present invention can be widely used in the structure of constructing a latch, and is suitable for fields with high requirements on the reliability and comprehensive cost of the latch.

The application discloses a kind of anti-single event upset DICE flip-flop reinforcement structures based on clocked gate. In view of the defect that the transmission gate in the conventional DICE flip-flop easily leads to the cross-loop propagation of single particle interference signal at the clock edge, the first stage transmission gate is optimized as an inverter combined with a clocked gate structure, which is composed of two series PMOS tubes (gates connected with clock CK and inverted signal respectively) and two series NMOS tubes (gates connected with clock CKN and inverted signal respectively). The overall structure includes a redundant clock input part, a data input control part, a main DICE structure latch loop, a main-slave loop connection control part, a slave DICE structure latch loop and an output driving part. This design can effectively block the conduction of interference signals between the double interlocking loops, while ensuring that the signal phase remains unchanged, greatly improving the radiation tolerance of the flip-flop. It is suitable for high-reliability integrated circuits in aerospace, nuclear power and other fields, with low cost and high reliability.

The embodiment of the invention discloses a cache missing request processing method and a missing state keeping register. A cache missing request management mode based on a linked list is combined with a cache missing request management mode based on class first-in first-out, and identification information is introduced to represent the entry state of a corresponding entry in the linked list, so that an entry which needs to be released currently is selected based on the identification information; according to the embodiment of the invention, on the premise of ensuring that the cache line missing requests for the same cache address are processed prior to the cache block missing requests, the cache missing requests are sequentially processed as much as possible according to the arrival sequence, and meanwhile, the area overhead caused by processing the cache missing requests is reduced.

The disclosure provides a shared memory interconnection device and arbitration method and arbitration circuit, relates to the technical field of integrated circuit interconnection, and realizes the scheme as follows: a layered interconnection network comprises an outer layer routing network and an inner layer switching network, the outer layer routing network comprises a multi-stage switching network composed of a plurality of butterfly-shaped switching units, is used for routing data flow groups of input ports to a plurality of subgroups of the inner layer switching network, the inner layer switching network comprises a plurality of crossbar switch switching modules, and is used for executing local non-blocking switching; an arbitration module maintains the weight values of the input ports, determines an arbitration result based on the weight values between the ports in conflict, increases the weight value of the corresponding port by a preset increment when the arbitration fails, restores the weight value of the corresponding port to an initial value when the arbitration succeeds, and the arbitration result of each port is determined by cascading the arbitration states between the ports in conflict, so that the local bandwidth and low delay can be guaranteed while the hardware area overhead is greatly reduced.

The invention provides an FIFO circuit and electronic equipment, and relates to the technical field of circuit design. In the FIFO circuit, an input cache module comprises n input registers and is used for receiving n pieces of to-be-stored target data output by an upstream circuit; the storage module comprises a storage controller and a memory, the memory is divided into n virtual FIFOs, and the n virtual FIFOs are in one-to-one correspondence with the n input registers; the first address management module is used for determining a virtual FIFO meeting a first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock cycle, generating a corresponding write address of a write pointer of the first virtual FIFO in the memory, sending the write address to the memory controller, and sending the write address to the memory controller; a first input register corresponding to the first virtual FIFO is controlled to output target data to a storage controller; the memory controller is to write the target data to the memory based on the write address. According to the invention, the occupied area of the whole circuit of a plurality of FIFOs can be effectively reduced, and the efficiency of the whole area is improved.

The present application relates to the technical field of in-memory computing, and particularly relates to an in-memory computing circuit, an in-memory writable multiplication computing circuit and a chip. The in-memory computing circuit comprises a weight layer, a computing layer, a first storage layer and a second storage layer arranged in sequence from top to bottom. The weight layer is used for storing binary weights. The computing layer is used for performing multiplication operation on the binary weights input from outside and the binary weights stored in the weight layer. The first storage layer is used for storing high four-bit operation results. The second storage layer is used for storing low four-bit operation results. When the in-memory computing circuit performs multiplication operation, the multiplication operation on the four-bit weights input by the input signal line IN_B and the four-bit weights stored in the weight layer is split into four-period addition operation, and the operation results are stored in the first storage layer and the second storage layer. The circuit of the present application introduces multiplication from analog domain-based operation to digital domain-based operation, and stores the operation results, thereby avoiding the problems encountered in analog domain multiplication.

The application discloses a terminal circuit with bandwidth expansion and impedance matching functions, and belongs to the technical field of basic electronic circuits. In view of the defects in the prior art, the terminal circuit is designed by adopting a simplified three-stage asymmetric T-coil technology, and the terminal circuit comprises a first pad capacitor, a second pad capacitor, a first impedance matching module, a first bandwidth expansion module based on a three-stage asymmetric T-coil structure, a second impedance matching module, a second bandwidth expansion module based on the three-stage asymmetric T-coil structure, a first terminal resistor, a second terminal resistor and a load circuit. The terminal circuit can greatly enhance the bandwidth expansion capability, uses a small number of inductors and capacitors, has a good impedance matching effect, and realizes a great reduction of area overhead. Meanwhile, the application has high engineering applicability, is suitable for engineering product design, can be widely used in the design of a SerDes analog front end, can greatly improve the performance index of the analog front end, and simultaneously reduces comprehensive overhead.

This application relates to a system for high-efficiency bit-serial in-memory multiplication and a 5-3 compressor circuit. The 5-3 compressor circuit includes two mirror adders. This circuit refactors the full adder core, decomposing it into independent carry-generating and sum-generating modules. The output of the carry-generating module depends entirely on the initial input, while the output of the sum-generating module depends on both the initial input and the output of the carry-generating module. The refactored adders reduce area overhead. Using the two refactored adders to form the 5-3 compressor circuit results in a critical path containing only 4 stages of transistor delay, intersecting with a conventional implementation consisting of two cascaded 3-2 compressors (6 stages of delay in total). This circuit reduces the area overhead of two inverters (4T) while achieving the same delay overhead as a single 3-2 compressor.

This invention discloses a bit-loading-based HPLC signal processing method, belonging to the field of power line carrier communication technology. The bit-loading-based HPLC signal processing method includes: reading bit data from a channel interleaving module and sequentially writing it into a first bit buffer queue according to a preset number of bits to be read from the channel interleaving module; in bit-loading mode, determining the target number of bits to be filled for each subcarrier based on the modulation scheme corresponding to each subcarrier; different modulation schemes correspond to different target bit numbers; sequentially reading the target number of bits from the first bit buffer queue according to the writing order, and mapping the read-out bit data to the corresponding subcarrier for modulation and transmission. This invention achieves efficient rate matching for data processing in bit-loading mode and data transmission without subcarriers crossing physical blocks.

The application discloses an address remapping device, method and processor, and the device comprises: a first calculation module which takes the complement of the low L bits of an original logical address to obtain a complement result; a second calculation module which dynamically obtains an offset correction value which keeps the order of an output channel group according to the original logical address; a third calculation module which determines the base address offset across the input channel group; a fourth calculation module which performs summation and one addition operation on the complement result and the offset correction value, and extracts the low L bits to obtain a local logical address; and finally, an address composition module which adds the local logical address and the base address offset to generate a target logical address corresponding to the original logical address. In the memory access path, the application can efficiently realize the 180° rotation of the convolution kernel at the hardware level through additional processing of the address, so as to fundamentally eliminate the efficiency loss caused by the software rotation.

This disclosure provides a data access method, system, device, storage medium, and program product. The data access method includes: receiving a current memory access request; associating the current memory access request with in-transit memory access requests in a preset storage area; in response to a first in-transit memory access request that has an association, establishing an association between the current memory access request and the first in-transit memory access request, and storing the current memory access request as an in-transit memory access request in a free storage space in the preset storage area; in response to receiving read data corresponding to a second in-transit memory access request, returning the read data as the target memory access data for the second in-transit memory access request; obtaining a third in-transit memory access request associated with the second in-transit memory access request based on the association, extracting the target memory access data corresponding to the third in-transit memory access request from the read data, and returning it. This disclosure can effectively reduce the number of memory accesses, improving the utilization rate of the memory access bus bandwidth while reducing system power consumption.

This invention discloses a high-precision time-to-digital converter based on multi-level quantization, comprising: a counter for coarse quantization of a time signal to obtain a reference number of cycles included in the time signal; a start signal channel for intermediate quantization of a first remaining time using a first delay chain to obtain a first internal number of cycles, and fine quantization of the first remaining time by multiplexing the first delay chain into a ring oscillator to obtain a first residual quantization result; and a stop signal channel for obtaining a second residual quantization result and a second internal number of cycles through a similar process. According to the high-precision time converter provided by this invention, by multiplexing the delay chain into a ring oscillator to fine quantize the residual time instead of using two delay chains to quantize the time signal, the delay difference generated by two delay chains can be avoided, thereby improving the efficiency of time signal quantization; at the same time, by multiplexing the delay chains, the area overhead can be reduced, simplifying the structure of the high-precision time converter.

The invention discloses a nonlinear compensation circuit of an analog-to-digital converter input buffer. In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the input buffer buffers the input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from a sampling switch; the common-mode buffer buffers the common-mode voltage of the analog-to-digital converter; the input end of a current replication circuit is connected to the gate end and the drain end of a top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common-mode buffer, so that the top transistor of the input buffer and the top transistor of the common-mode buffer form a current mirror; the sampling circuit is composed of a sampling switch and a sampling capacitor, the upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, the lower plate of the sampling capacitor is connected to the output of the common-mode buffer, and after the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to a reference voltage, the sampling capacitor maintains the voltage difference between the input signal and the common-mode signal, and sends it to a comparator.

The application relates to the technical field of integrated circuits, in particular to a duty cycle adjustment circuit capable of keeping the rising edge fixed delay. The duty cycle adjustment circuit comprises a first delay line module, a second delay line module, a logic operation unit, a first or logic operation unit and a multiplexer. The first input end and the second input end of the first delay line module are connected with a first delay control signal and an external input clock signal respectively, and the output of the first delay line module is a first delay clock signal. The first input end and the second input end of the second delay line module are connected with a second delay control signal and the external input clock signal respectively, and the output of the second delay line module is a second delay clock signal. The first input end and the second input end of the logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the logic operation unit is a clock and signal. The first input end and the second input end of the first or logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the first or logic operation unit is a clock or signal. The first input end and the second input end of the multiplexer are connected with the clock and signal and the clock or signal respectively, and the multiplexer is used for controlling the output of the clock and signal or the clock or signal according to a symbol bit signal. The application can accurately correct the duty cycle.

The invention discloses a data transmission system, method and device and a computer program product, and relates to the technical field of integrated circuits, and the system comprises an APB interface which is used for obtaining a transmission signal of APB equipment; the AHB interface is used for acquiring a transmission signal of AHB equipment; and the data conversion module jumps to a signal configuration state based on the high-level chip selection signal and the transmission response signal as well as the low-level enable signal. According to the technical scheme, data transmission management between the APB device and the AHB device is achieved, the redundant transmission time is shortened, the data transmission efficiency is improved, meanwhile, the configured working state only needs to occupy few register resources, and the area overhead of a bus matrix is reduced.

The present application relates to the technical field of integrated circuits, and further to a memory test and repair system and method, and an integrated circuit. The system comprises: a memory array with redundant columns; a first controller comprises: a first control unit receives a first test signal in a first test mode and outputs a first test control signal; a second control unit receives a second test signal in a second test mode and outputs a second test control signal; a second controller receives the first / second test control signal and generates a third test control signal; traverses the test memory array under the third test control signal, and feeds back the first test result to the first controller; compares and analyzes and outputs the second test result; the third controller analyzes the second test result and obtains fault information; the fourth controller analyzes the fault information and outputs a repair control signal to the memory array, and the memory array is repaired in an address reconstruction manner. The system saves hardware resources and test time.

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

The invention discloses a function safety test circuit and method, a neural network processor and a storage medium, and relates to the technical field of function safety, and the function safety test circuit comprises a configurator which is used for generating and outputting configuration information for testing a to-be-tested integrated circuit; the plurality of test data generators are used for generating and outputting first test data respectively corresponding to each test data generator in the plurality of test data generators based on the configuration information; the to-be-tested integrated circuit is used for processing the plurality of first test data to obtain and output a plurality of second test data; and the first comparator is used for comparing the consistency of the plurality of second test data to obtain a first test result of the integrated circuit to be tested. According to the technical scheme, the whole to-be-tested integrated circuit can be covered, the expected functional safety standard requirement is met, parity check bits do not need to be added to the transmission data of the to-be-tested integrated circuit, the area overhead can be saved, and the transmission power consumption can be reduced.

The application discloses a chip function safety verification system based on hierarchical explainable graph learning, comprising: a feature extraction module for parsing a gate-level netlist to extract a cell-level feature; a hypergraph construction module for dividing fan-out-free regions based on a dominating node and aggregating into super nodes to construct a hypergraph structure; a hierarchical graph learning module for constructing a gate-level and super node-level double-layer network to capture local topology dependence and global fault propagation and output a fault critical region prediction; and an explainability analysis and reinforcement module for locating the core gate unit with the highest contribution in the critical region and generating a hierarchical safety reinforcement scheme. The application realizes accurate prediction and explainable positioning of the fault critical region through hierarchical graph learning, and significantly improves verification efficiency and accuracy.

The invention discloses a multi-interface protocol audio coding and decoding chip control channel system and method, terminal equipment and a storage medium, the system comprises a mapping module, a plurality of audio modules and a plurality of protocol interface modules, each protocol interface module comprises an interface, and the interface in each protocol interface module has a corresponding interface protocol; wherein the protocol interface module is used for acquiring an access request received by an interface in the module and analyzing the acquired access request based on an interface protocol corresponding to the interface in the module to generate a protocol address; the mapping module is used for mapping the protocol address analyzed and generated by the protocol interface module into an access address with a unified coding standard, and transmitting the access address obtained by mapping to the corresponding audio module; different audio modules have different access addresses; and the audio module is used for receiving the access address transmitted by the mapping module and providing a corresponding access function. Therefore, the area overhead of the audio coding and decoding chip can be effectively reduced, and the cost is greatly saved.

The present invention relates to the technical field of convolutional neural networks, and discloses a data processing method, device and chip based on a sensing-storage-computing integrated architecture, the method is used to process the convolution calculation of the input matrix [A1, A2, ..., AM] of M×N input data, the size of the convolution kernel W is k, the step length is s, and the method includes the following loop steps: constructing an input submatrix Yi, forming a reorganized convolution kernel Wi, Yi and Wi convolution calculation, and judging whether the loop is completed. The method, device and chip of the present invention can effectively reduce the number of analog registers required for convolution operations in a sensing-storage-computing integrated chip by cyclically controlling the input and weights, greatly reducing the area, cost and power consumption of the sensing-storage-computing chip, and improving the calculation speed.

The application belongs to the field of integrated circuit technology design, and relates to a passive and crystal-free GFSK transmitter chip, which comprises a radio frequency energy collection module, a power management module, a clock recovery module and an open-loop modulation transmitter module, the radio frequency energy collection module is used for wireless power supply, the power management module controls a power switch of the transmitter chip according to a power supply voltage value, when the power switch is opened, the power management module supplies power to the open-loop modulation transmitter module, the clock recovery module provides a reference frequency for the open-loop modulation transmitter module, and the open-loop modulation transmitter module multiplies the reference frequency to a radio frequency frequency required for transmission and transmits a data signal. The transmitter chip has the advantages of low power consumption and small size, is suitable for wireless sensor network nodes, and has strong commercial value.

The present invention relates to the field of chip design, and in particular to a dynamic mapping method, electronic device and storage medium for multi-bank access, which obtains the address of a target memory bank bank0 by parsing an access request command cmd0; if the number of state machines currently allocated to a bank is greater than a preset allocation threshold, a mapping relationship between bank0 and a target state machine FSM0 is established through dynamic mapping, and the steps of dynamic mapping include: if there is a state machine with an unallocated bank, a state machine FSM0 of an unallocated bank is allocated to bank0, and a mapping relationship between FSM0 and bank0 is established; and at the same time, the state machine FSM0 is released. i With bank i The mapping relationship between them is used to obtain the state machine FSM of the unassigned bank. i It reduces area overhead and also improves the timing of logic design.

This invention discloses a fast modular multiplication method and modular multiplier based on homomorphic encryption, belonging to the field of lattice cryptography. The method first calculates the product of the multiplicands, performs multiple shifts and reductions under a congruent environment, and finally compares the result with the modulus for a final reduction step to obtain the final modular multiplication result. The modular multiplier includes a modular arithmetic module, a modular multiplication module, and a control and output module. The purpose of this invention is to overcome the problems of existing modular multiplication algorithms based on homomorphic encryption involving numerous multiplication calculations, high computational complexity, and long computation time. This invention can reduce computational complexity, accelerate computation speed, and reduce hardware area overhead.

The embodiment of the specification provides an optical sensing system and a digital sampling signal calculation method. The system comprises a slope signal generator, a digital logic circuit and a plurality of column circuits; the slope signal generator is used to generate a slope signal and transmit the slope signal to the column circuits; the slope signal comprises a signal with gradually changing signal strength over time, and the signal strength change speed of the slope signal corresponds to the amplification multiple of a photosensitive electric signal; one of the plurality of column circuits is used to receive the photosensitive electric signal, and output a photosensitive gain signal to the digital logic circuit according to the slope signal and the photosensitive electric signal; the photosensitive gain signal comprises a digital signal corresponding to the photosensitive electric signal after signal strength amplification; and the digital logic circuit is used to calculate a digital sampling signal according to the photosensitive gain signal. The above system reduces the area overhead of the chip corresponding to the optical sensing system, and improves the application range of the corresponding optical sensing chip.

The invention discloses a low-voltage low-temperature-drift band-gap reference voltage source circuit. The circuit comprises a starting circuit, a band gap core circuit and a high-order temperature compensation circuit. In a low-voltage band gap core based on a Banba structure, offset voltage is actively eliminated through a chopping amplifier so as to suppress process deviation; meanwhile, a positive temperature coefficient voltage signal generated by the core loop is multiplexed and input into a high-order temperature compensation module, a nonlinear second-order compensation current activated only in an extreme temperature interval is generated, and the current is accurately injected into a specific node of an output resistance network. According to the compensation module, through a temperature coefficient current extractor and two adjusting channels with temperature selectivity, efficient and low-overhead offset of a bipolar transistor VBE high-order nonlinear temperature item is realized. According to the circuit, the static power consumption and the chip area are hardly increased while the temperature drift coefficient is remarkably reduced, and the circuit has excellent process deviation suppression capability.

The invention relates to an in-memory multiplication circuit and module of an SRAM (Static Random Access Memory), the SRAM and electronic equipment, the in-memory multiplication circuit comprises a storage part and a weighting part, the storage part comprises eight storage units, each storage unit is provided with an analog quantity input end and an analog quantity output end and is used for storing a single bit weight, and the weighting part is used for weighting the analog quantity input end and the analog quantity output end. The analog input end and the analog output end of each storage unit are conducted when the single bit weight stored in the storage unit is 1, and the analog input end and the analog output end of each storage unit are disconnected when the single bit weight stored in the storage unit is 0; the weighting part comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor. The number and the total capacitance value of the adopted capacitors are smaller, the area overhead of the circuit is reduced, and the problem that the area overhead of an existing in-memory multiplication circuit of the SRAM based on the charge domain is large is solved.

The invention discloses an on-chip temperature sensing method for monitoring heat distribution of an integrated circuit, belongs to the technical field of semiconductors, and aims to solve the problems of insufficient temporal-spatial resolution, large thermal field reconstruction deviation, high hardware overhead and the like in the prior art. According to the method, a microstructure thermal response unit composed of a high-thermal-conductivity metal layer and a low-thermal-capacity dielectric layer is embedded in a chip, a thermal time constant of the microstructure thermal response unit serves as a dynamic sensing parameter, and a three-level framework of a basic sensing layer, a regional polymerization layer and a global coordination layer is constructed; and in combination with pulse heating-cooling time sequence measurement, weighted fusion based on heat flow continuity constraint and a data assimilation algorithm based on partial differential equation constraint, high-precision real-time reconstruction of the three-dimensional temperature field is realized. According to the scheme, additional process masks are not needed, the area overhead is lower than 0.5%, and the submillimeter-level space resolution and the microsecond-level time resolution are both achieved.