17results about How to "Small area overhead" patented technology

The application discloses a kind of anti-single event upset DICE flip-flop reinforcement structures based on clocked gate. In view of the defect that the transmission gate in the conventional DICE flip-flop easily leads to the cross-loop propagation of single particle interference signal at the clock edge, the first stage transmission gate is optimized as an inverter combined with a clocked gate structure, which is composed of two series PMOS tubes (gates connected with clock CK and inverted signal respectively) and two series NMOS tubes (gates connected with clock CKN and inverted signal respectively). The overall structure includes a redundant clock input part, a data input control part, a main DICE structure latch loop, a main-slave loop connection control part, a slave DICE structure latch loop and an output driving part. This design can effectively block the conduction of interference signals between the double interlocking loops, while ensuring that the signal phase remains unchanged, greatly improving the radiation tolerance of the flip-flop. It is suitable for high-reliability integrated circuits in aerospace, nuclear power and other fields, with low cost and high reliability.

The embodiment of the invention discloses a cache missing request processing method and a missing state keeping register. A cache missing request management mode based on a linked list is combined with a cache missing request management mode based on class first-in first-out, and identification information is introduced to represent the entry state of a corresponding entry in the linked list, so that an entry which needs to be released currently is selected based on the identification information; according to the embodiment of the invention, on the premise of ensuring that the cache line missing requests for the same cache address are processed prior to the cache block missing requests, the cache missing requests are sequentially processed as much as possible according to the arrival sequence, and meanwhile, the area overhead caused by processing the cache missing requests is reduced.

The invention provides an FIFO circuit and electronic equipment, and relates to the technical field of circuit design. In the FIFO circuit, an input cache module comprises n input registers and is used for receiving n pieces of to-be-stored target data output by an upstream circuit; the storage module comprises a storage controller and a memory, the memory is divided into n virtual FIFOs, and the n virtual FIFOs are in one-to-one correspondence with the n input registers; the first address management module is used for determining a virtual FIFO meeting a first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock cycle, generating a corresponding write address of a write pointer of the first virtual FIFO in the memory, sending the write address to the memory controller, and sending the write address to the memory controller; a first input register corresponding to the first virtual FIFO is controlled to output target data to a storage controller; the memory controller is to write the target data to the memory based on the write address. According to the invention, the occupied area of the whole circuit of a plurality of FIFOs can be effectively reduced, and the efficiency of the whole area is improved.

The present application relates to the technical field of in-memory computing, and particularly relates to an in-memory computing circuit, an in-memory writable multiplication computing circuit and a chip. The in-memory computing circuit comprises a weight layer, a computing layer, a first storage layer and a second storage layer arranged in sequence from top to bottom. The weight layer is used for storing binary weights. The computing layer is used for performing multiplication operation on the binary weights input from outside and the binary weights stored in the weight layer. The first storage layer is used for storing high four-bit operation results. The second storage layer is used for storing low four-bit operation results. When the in-memory computing circuit performs multiplication operation, the multiplication operation on the four-bit weights input by the input signal line IN_B and the four-bit weights stored in the weight layer is split into four-period addition operation, and the operation results are stored in the first storage layer and the second storage layer. The circuit of the present application introduces multiplication from analog domain-based operation to digital domain-based operation, and stores the operation results, thereby avoiding the problems encountered in analog domain multiplication.

The application discloses a terminal circuit with bandwidth expansion and impedance matching functions, and belongs to the technical field of basic electronic circuits. In view of the defects in the prior art, the terminal circuit is designed by adopting a simplified three-stage asymmetric T-coil technology, and the terminal circuit comprises a first pad capacitor, a second pad capacitor, a first impedance matching module, a first bandwidth expansion module based on a three-stage asymmetric T-coil structure, a second impedance matching module, a second bandwidth expansion module based on the three-stage asymmetric T-coil structure, a first terminal resistor, a second terminal resistor and a load circuit. The terminal circuit can greatly enhance the bandwidth expansion capability, uses a small number of inductors and capacitors, has a good impedance matching effect, and realizes a great reduction of area overhead. Meanwhile, the application has high engineering applicability, is suitable for engineering product design, can be widely used in the design of a SerDes analog front end, can greatly improve the performance index of the analog front end, and simultaneously reduces comprehensive overhead.

This application relates to a system for high-efficiency bit-serial in-memory multiplication and a 5-3 compressor circuit. The 5-3 compressor circuit includes two mirror adders. This circuit refactors the full adder core, decomposing it into independent carry-generating and sum-generating modules. The output of the carry-generating module depends entirely on the initial input, while the output of the sum-generating module depends on both the initial input and the output of the carry-generating module. The refactored adders reduce area overhead. Using the two refactored adders to form the 5-3 compressor circuit results in a critical path containing only 4 stages of transistor delay, intersecting with a conventional implementation consisting of two cascaded 3-2 compressors (6 stages of delay in total). This circuit reduces the area overhead of two inverters (4T) while achieving the same delay overhead as a single 3-2 compressor.

This invention discloses a bit-loading-based HPLC signal processing method, belonging to the field of power line carrier communication technology. The bit-loading-based HPLC signal processing method includes: reading bit data from a channel interleaving module and sequentially writing it into a first bit buffer queue according to a preset number of bits to be read from the channel interleaving module; in bit-loading mode, determining the target number of bits to be filled for each subcarrier based on the modulation scheme corresponding to each subcarrier; different modulation schemes correspond to different target bit numbers; sequentially reading the target number of bits from the first bit buffer queue according to the writing order, and mapping the read-out bit data to the corresponding subcarrier for modulation and transmission. This invention achieves efficient rate matching for data processing in bit-loading mode and data transmission without subcarriers crossing physical blocks.

The application discloses an address remapping device, method and processor, and the device comprises: a first calculation module which takes the complement of the low L bits of an original logical address to obtain a complement result; a second calculation module which dynamically obtains an offset correction value which keeps the order of an output channel group according to the original logical address; a third calculation module which determines the base address offset across the input channel group; a fourth calculation module which performs summation and one addition operation on the complement result and the offset correction value, and extracts the low L bits to obtain a local logical address; and finally, an address composition module which adds the local logical address and the base address offset to generate a target logical address corresponding to the original logical address. In the memory access path, the application can efficiently realize the 180° rotation of the convolution kernel at the hardware level through additional processing of the address, so as to fundamentally eliminate the efficiency loss caused by the software rotation.

This disclosure provides a data access method, system, device, storage medium, and program product. The data access method includes: receiving a current memory access request; associating the current memory access request with in-transit memory access requests in a preset storage area; in response to a first in-transit memory access request that has an association, establishing an association between the current memory access request and the first in-transit memory access request, and storing the current memory access request as an in-transit memory access request in a free storage space in the preset storage area; in response to receiving read data corresponding to a second in-transit memory access request, returning the read data as the target memory access data for the second in-transit memory access request; obtaining a third in-transit memory access request associated with the second in-transit memory access request based on the association, extracting the target memory access data corresponding to the third in-transit memory access request from the read data, and returning it. This disclosure can effectively reduce the number of memory accesses, improving the utilization rate of the memory access bus bandwidth while reducing system power consumption.

This invention discloses a high-precision time-to-digital converter based on multi-level quantization, comprising: a counter for coarse quantization of a time signal to obtain a reference number of cycles included in the time signal; a start signal channel for intermediate quantization of a first remaining time using a first delay chain to obtain a first internal number of cycles, and fine quantization of the first remaining time by multiplexing the first delay chain into a ring oscillator to obtain a first residual quantization result; and a stop signal channel for obtaining a second residual quantization result and a second internal number of cycles through a similar process. According to the high-precision time converter provided by this invention, by multiplexing the delay chain into a ring oscillator to fine quantize the residual time instead of using two delay chains to quantize the time signal, the delay difference generated by two delay chains can be avoided, thereby improving the efficiency of time signal quantization; at the same time, by multiplexing the delay chains, the area overhead can be reduced, simplifying the structure of the high-precision time converter.

The application relates to the technical field of integrated circuits, in particular to a duty cycle adjustment circuit capable of keeping the rising edge fixed delay. The duty cycle adjustment circuit comprises a first delay line module, a second delay line module, a logic operation unit, a first or logic operation unit and a multiplexer. The first input end and the second input end of the first delay line module are connected with a first delay control signal and an external input clock signal respectively, and the output of the first delay line module is a first delay clock signal. The first input end and the second input end of the second delay line module are connected with a second delay control signal and the external input clock signal respectively, and the output of the second delay line module is a second delay clock signal. The first input end and the second input end of the logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the logic operation unit is a clock and signal. The first input end and the second input end of the first or logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the first or logic operation unit is a clock or signal. The first input end and the second input end of the multiplexer are connected with the clock and signal and the clock or signal respectively, and the multiplexer is used for controlling the output of the clock and signal or the clock or signal according to a symbol bit signal. The application can accurately correct the duty cycle.

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

The application belongs to the field of integrated circuit technology design, and relates to a passive and crystal-free GFSK transmitter chip, which comprises a radio frequency energy collection module, a power management module, a clock recovery module and an open-loop modulation transmitter module, the radio frequency energy collection module is used for wireless power supply, the power management module controls a power switch of the transmitter chip according to a power supply voltage value, when the power switch is opened, the power management module supplies power to the open-loop modulation transmitter module, the clock recovery module provides a reference frequency for the open-loop modulation transmitter module, and the open-loop modulation transmitter module multiplies the reference frequency to a radio frequency frequency required for transmission and transmits a data signal. The transmitter chip has the advantages of low power consumption and small size, is suitable for wireless sensor network nodes, and has strong commercial value.

This invention discloses a fast modular multiplication method and modular multiplier based on homomorphic encryption, belonging to the field of lattice cryptography. The method first calculates the product of the multiplicands, performs multiple shifts and reductions under a congruent environment, and finally compares the result with the modulus for a final reduction step to obtain the final modular multiplication result. The modular multiplier includes a modular arithmetic module, a modular multiplication module, and a control and output module. The purpose of this invention is to overcome the problems of existing modular multiplication algorithms based on homomorphic encryption involving numerous multiplication calculations, high computational complexity, and long computation time. This invention can reduce computational complexity, accelerate computation speed, and reduce hardware area overhead.

The embodiment of the specification provides an optical sensing system and a digital sampling signal calculation method. The system comprises a slope signal generator, a digital logic circuit and a plurality of column circuits; the slope signal generator is used to generate a slope signal and transmit the slope signal to the column circuits; the slope signal comprises a signal with gradually changing signal strength over time, and the signal strength change speed of the slope signal corresponds to the amplification multiple of a photosensitive electric signal; one of the plurality of column circuits is used to receive the photosensitive electric signal, and output a photosensitive gain signal to the digital logic circuit according to the slope signal and the photosensitive electric signal; the photosensitive gain signal comprises a digital signal corresponding to the photosensitive electric signal after signal strength amplification; and the digital logic circuit is used to calculate a digital sampling signal according to the photosensitive gain signal. The above system reduces the area overhead of the chip corresponding to the optical sensing system, and improves the application range of the corresponding optical sensing chip.

The invention discloses a low-voltage low-temperature-drift band-gap reference voltage source circuit. The circuit comprises a starting circuit, a band gap core circuit and a high-order temperature compensation circuit. In a low-voltage band gap core based on a Banba structure, offset voltage is actively eliminated through a chopping amplifier so as to suppress process deviation; meanwhile, a positive temperature coefficient voltage signal generated by the core loop is multiplexed and input into a high-order temperature compensation module, a nonlinear second-order compensation current activated only in an extreme temperature interval is generated, and the current is accurately injected into a specific node of an output resistance network. According to the compensation module, through a temperature coefficient current extractor and two adjusting channels with temperature selectivity, efficient and low-overhead offset of a bipolar transistor VBE high-order nonlinear temperature item is realized. According to the circuit, the static power consumption and the chip area are hardly increased while the temperature drift coefficient is remarkably reduced, and the circuit has excellent process deviation suppression capability.

The invention discloses an on-chip temperature sensing method for monitoring heat distribution of an integrated circuit, belongs to the technical field of semiconductors, and aims to solve the problems of insufficient temporal-spatial resolution, large thermal field reconstruction deviation, high hardware overhead and the like in the prior art. According to the method, a microstructure thermal response unit composed of a high-thermal-conductivity metal layer and a low-thermal-capacity dielectric layer is embedded in a chip, a thermal time constant of the microstructure thermal response unit serves as a dynamic sensing parameter, and a three-level framework of a basic sensing layer, a regional polymerization layer and a global coordination layer is constructed; and in combination with pulse heating-cooling time sequence measurement, weighted fusion based on heat flow continuity constraint and a data assimilation algorithm based on partial differential equation constraint, high-precision real-time reconstruction of the three-dimensional temperature field is realized. According to the scheme, additional process masks are not needed, the area overhead is lower than 0.5%, and the submillimeter-level space resolution and the microsecond-level time resolution are both achieved.