Self-recovery single particle resistance latch register structure based on time-delay unit

Abstract

The invention discloses a self-recovery single particle resistance latch register structure based on a time-delay unit, comprising two clock-control inverter structures, four dual-input inverter structures, two transmission gate structures, one time delay unit and a C unit structure; the four dual-input inverter structures constitute a dual-mode interlocking structure to realize self-recovery of the single event upset (SEU); the time delay unit structure and an C unit constitute a filtering structure to block the single event transient (SET) coming from the combination logic circuit. The invention can tolerate the SEU happened in the latch register structure and the SET transmitted from the logic circuit, has the self-recovery function, has a simple circuit, reduces the consumption of the area, reduces the power consumption and improves the system reliability.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the field of anti-radiation reinforcement design of integrated circuits, in particular to a self-recovery anti-single event latch structure based on a delay unit. Background technique [0002] With the continuous development of integrated circuits (IC), the process size and power supply voltage continue to decrease. In IC design, while providing lower power consumption and higher performance, higher requirements are placed on the stability of the chip. . Especially in some special environments such as space, etc., the impact of high-energy particle beams such as alpha particle beams and neutrons may induce single event effects (SingleEventEffect, SEE) in the circuit, which will cause errors in the circuit state, and in severe cases will lead to The system crashes. [0003] Among them, Single Event Upset (SingleEventUpset, SEU) and Single Event Transient (SingleEventTran...

AI Technical Summary

Problems solved by technology

Most traditional hardened latch designs use C-cell circuits to shield soft errors. When particles bombard the input of C-cell circuits, the output node can easily enter a high-impedance state, which in turn causes soft errors due to leakage currents.

Therefore, these latches do not have a self-recovery function and cannot be applied to gated clock circuits

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