11results about How to "Reduce power overhead" patented technology

The application provides a near-memory DMA data transposition controller, a data transposition method, a medium and a product. The near-memory DMA data transposition controller is arranged on a data transmission path between a far-end memory and a near-end memory of an AI computing chip, and comprises a first DMA control module and a second DMA control module. The transposition operation only occurs after data is read from the near-end memory, thereby reducing independent transposition processing links, reducing transposition power consumption overhead and operation delay, avoiding a decrease in bus bandwidth utilization caused by transposition, and reducing hardware resource overhead. A dynamic splitting strategy concentrates non-aligned access in a first data block, thereby improving overall bandwidth utilization. The transposition operation is separated from a computing unit, the transposition is completed synchronously in a data carrying process, computing resources are released, and an operation period and power consumption overhead are reduced.

This invention relates to the field of integrated circuits and discloses a mixed-precision in-memory computing circuit, data processing method, and chip. The invention includes: a storage array, an index memory, and a multiply-accumulate calculation circuit. The storage array includes a first data element stored in a first precision format and / or a second data element stored in a second precision format; wherein the bit width of the first precision format is greater than that of the second precision format; the storage locations of the storage array are divided according to the bit width of the second precision format; the first data element occupies multiple consecutive storage locations; the read bit width of the storage array is an integer multiple of the bit width of the first precision format; the index memory stores the position index information of the first data element in the storage array; the multiply-accumulate calculation circuit is used to determine the precision format corresponding to the data read from the storage array based on the position index information, and performs a multiply-accumulate operation corresponding to the precision format, outputting the calculation result. This solves the compatibility problem between mixed-precision data storage and computing circuits.

This application belongs to the interdisciplinary fields of semiconductor optoelectronic devices, multiferroic materials, and neuromorphic computing. Specifically, it discloses an in-situ differential optoelectronic synaptic device and its in-memory computing method. The method involves grounding the first and second electrodes, applying a voltage to the bottom electrode to change the polarization direction of the ferroelectric domains in the bismuth ferrite thin film, and using the polarization direction of the ferroelectric domains as the weight symbol in the neural weights to set the non-volatile synaptic weights. The voltage on the bottom electrode is then removed or reduced, and a light spot is used to illuminate the bismuth ferrite thin film. By adjusting the position of the light spot, the differential current between the first and second electrodes is read and used as the weight value in the neural weights, thus realizing the read operation. This application achieves integrated storage and computing.

The application provides a kind of spaceborne super high speed image intelligent processing method and device, including: high speed data interface unit, intelligent image processing unit, main control unit;The high speed data interface unit is connected respectively external data input unit, intelligent image processing unit and main control unit.This application keeps original data on front end FPGA, GPU module is only used as the position calculation of slice, avoids the repeated transmission of internal mass data, so as to cause the pressure of transmission bandwidth.

The invention relates to the field of signal processing and the technical field of semiconductor integrated circuits, in particular to a storage and calculation integrated MIMO precoding circuit, a storage and calculation integrated MIMO precoding method, an operation framework and a communication system. Comprising two groups of novel memory arrays, an operational amplifier, a voltage phase inverter, a current phase inverter and a trans-impedance amplifier, the first novel memory array comprises a first sub-array, a second sub-array and a third sub-array, and the second novel memory array comprises a fourth sub-array and a fifth sub-array; the second sub-array is connected with the third sub-array through the voltage phase inverter, and the fifth sub-array is connected with the trans-impedance amplifier through the current phase inverter. The two novel memory arrays cooperatively work in the same analog calculation loop, so that the circuit directly outputs a pre-coding result in a steady state, and sampling hold, interface buffer and additional control logic required by cascade connection of multi-stage modules in the prior art are avoided, thereby reducing system time delay and power consumption overhead.

The application discloses a reconfigurable digital in-memory computing device based on a multiplexed Booth computing unit and a 6T-SRAM. The device comprises 64 Booth multiplication in-memory computing processors. Each Booth multiplication in-memory computing processor comprises an in-memory computing array, and the in-memory computing array comprises a Booth multiplication in-memory computing data block, the Booth multiplication in-memory computing data block comprises an SRAM subarray and a Booth computing unit. The in-memory computing array has two working modes, namely a storage mode and a computing mode. In the storage mode, the in-memory computing array stores weight data input from outside. In the computing mode, the Booth multiplication in-memory computing processor outputs a 20-bit convolution computing result. The application supports configurable convolution computing scales, can flexibly cope with convolution neural network computing acceleration applications of different scales, improves the utilization rate of the in-memory computing array, and has the characteristics of high throughput and high energy efficiency.

The invention provides a key path monitoring point screening method and system combining a path activation rate and similarity, and the method comprises the steps: obtaining the time sequence information of all paths of a target circuit based on static time sequence analysis, screening out the paths with the time sequence allowance smaller than a threshold value according to the preset time sequence allowance threshold value, and forming a key path set; on the basis of a preset benchmark test set, signal overturning statistics is conducted on monitoring points of all paths in the key path set, the activation rate of all the paths is calculated, the paths with the activation rate being zero are filtered out, and an effective path set is obtained; grouping the paths in the effective path set according to starting points of the paths to obtain a plurality of path groups; for each path group, calculating the similarity between the paths based on the logic topological structure sequence of the paths in the group, clustering the paths according to the similarity, and screening out at least one path from each cluster; and summarizing the paths obtained after screening of all the path groups to form a final monitoring point set.

This invention provides a low-noise amplifier and electronic device for a phased array system, relating to the field of antenna technology. The input common-gate transistor is connected to the output common-gate transistor via an inductor-coupled transformer. The inductor-coupled transformer increases the transconductance of both the input and output common-gate transistors by utilizing the mutual coupling of its multiple inductors and adjusting the coupling coefficients between pairs of inductors. As the radio frequency signal is amplified by the input and output common-gate transistors with increased transconductance, noise is reduced, and the signal is then output to the subsequent circuitry by the output common-gate transistor. This invention achieves increased transconductance of the dual transistors, reduced noise figure, increased circuit gain, excellent circuit performance, and simplified input and noise matching. It also improves system integration, reduces chip area and power consumption, and indirectly reduces the cost of radio frequency millimeter-wave phased array systems.

The invention discloses an instruction transmission processing device and an instruction transmission processing method of a sequential multi-transmission processor. The device comprises an instruction extraction unit, an instruction processing unit and a processing unit, wherein the instruction extraction unit is used for reading an instruction block from an instruction memory and pre-decoding the instruction block to form a transmittable instruction block; the instruction decoding module is used for decoding the instruction blocks received from the instruction extraction unit to obtain information of each instruction to be processed; the instruction emission validity arbitration module adopts a full associative storage structure and comprises a plurality of entries, and state information of an instruction is stored in each entry; the emission queue module is connected with the instruction emission validity arbitration module and is used for caching the to-be-emitted instruction passing arbitration; the execution unit is connected with the emission queue module and is used for executing the instruction and writing an execution result back to a corresponding entry of the instruction emission validity arbitration module; the hardware area is small, the processing efficiency is high, and pipeline pause can be avoided by distinguishing processing according to the type of the preorder instruction.

The application provides a transformer neural network acceleration device based on a photoelectric storage and calculation integrated device and a method thereof.The device comprises: (1) an encoding module comprising: a multi-head attention calculation submodule for performing a multi-head attention calculation operation on an input vector; a feedforward fully connected layer submodule for performing a fully connected operation and a linear rectification operation; an addition unit for adding the input vector and the output vector in the upper module; a normalization submodule for performing a normalization operation on the input vector from the addition unit; (2) a decoding module comprising: a multi-head attention calculation submodule, a feedforward fully connected layer submodule, an addition unit and a normalization submodule; (3) a classification prediction module for performing a fully connected operation on a one-dimensional vector output by the upper module and performing a classification output operation.The device of the application can accelerate the implementation of the transformer neural network and greatly reduce the power consumption, area and calculation delay of the hardware architecture.

The present application relates to the technical field of data processing, and more particularly to a rescue protective helmet data acquisition method based on multi-source sensing, which comprises the following steps: collecting a plurality of sensing data and a plurality of vital sign data in real time, and constructing a time neighborhood at the current time; calculating a safety correlation degree for any kind of sensing data at the current time; calculating a risk feature to obtain a cooperative risk degree according to the difference of the relative mean value and the change of the local slope relative to the overall slope of the sensing data within the time neighborhood, and combining the risk feature sequence correlation and the safety correlation degree difference to calculate an auxiliary risk reference degree; weighting and fusing the cooperative risk degree by using the auxiliary risk reference degree to obtain a safety risk index, and multiplying the safety risk index by the obtained safety core degree to obtain a safety criticality; and weighting and correcting the basic sampling frequency by using the safety criticality to obtain a dynamic sampling frequency. The present application realizes the cooperative scheduling of multi-source sensing data, and solves the problems of sampling redundancy and risk identification lag.