24results about How to "Reduce power overhead" patented technology

The invention relates to the technical field of CPU card security chips, and discloses a low-power-consumption design method and system for a CPU card security chip, and the method comprises the steps: carrying out the current waveform sampling of a secret key storage region, an encryption operation unit and an identity authentication processor of the CPU card security chip, recording current data when the CPU card security chip executes data encryption, identity authentication and security calculation to obtain a feature parameter set of the security function module; establishing an encryption operation power consumption model and an identity authentication power consumption model, and obtaining power consumption characteristic matrixes under different key lengths through piecewise linear fitting; classifying the security application tasks to obtain a multi-level security task classification table; according to the multi-level security task classification table, a differential power consumption attack protection strategy is executed, the working voltage and frequency configuration sequence of each security function module is calculated, the optimal balance of power consumption and performance is achieved under different key lengths, and the comprehensive performance of the CPU card security chip is improved.

The invention discloses a decimal multi-modulus frequency divider circuit based on space-time averaging and phase interpolation technologies. The decimal multi-modulus frequency divider circuit comprises a third-order noise shaping modulation module, a dynamic element matching and phase selection module, a phase switching frequency divider module and a pipelined phase interpolation module. The third-order noise shaping modulation module is used for performing time averaging on the input frequency dividing ratio to generate an instantaneous frequency dividing ratio; the dynamic element matching and phase selection module is used for spatially averaging the instantaneous frequency dividing ratio and generating a frequency divider control word and a phase interpolator control word; the phase switching frequency divider module is used for generating a clock signal corresponding to a frequency dividing ratio according to the frequency divider control word; and the pipelined phase interpolation module is used for performing phase interpolation according to the clock signal to generate a final clock signal with an accurate phase. According to the embodiment of the invention, the mutual cooperation of the modules is utilized, the fusion of the space-time averaging technology and the phase interpolation technology is realized, and the limitation of the space-time averaging technology is improved.

The invention discloses a video processing system based on a domestic deep learning processor, which belongs to the field of video processing systems and comprises a multi-dimensional Bayesian optimization module, an unweighted neural network module and a space-time denoising and filtering module. The multi-dimensional Bayesian optimization module uses multi-dimensional Bayesian optimization to explore and optimize the design space of the deep learning processor; the unweighted neural network module is used for introducing an unweighted neural network in neural network design, and replacing traditional weighted connection with an LUT structure, so that the calculation overhead and power consumption of a processor are reduced; and the space-time denoising filtering module provides a group of space-time denoising filters connected with the cache, and filters noise events in the preprocessing of the video stream to improve the signal-to-noise ratio of the video data. According to the invention, by combining the power consumption advantage of hardware neurons and the lightweight design of the unweighted neural network, the calculation and power consumption overhead of the processor is greatly reduced, so that the processor can run on low-power-consumption edge equipment.

The invention discloses an information transmission method, a base station and user equipment. The information transmission method comprises the following steps: determining first downlink control information, the first downlink control information comprises at least one of the following information: indication information of a narrowband resource used by first information transmission, modulation coding method indication information of the first information transmission, frequency hopping indication information of the first information transmission, and coverage enhancement transmission indication information of the first information transmission; the first information comprises a random access response message and / or a paging message; and sending the first downlink control information to the UE, and sending the first information to the UE according to the first downlink control information.

The application provides a near-memory DMA data transposition controller, a data transposition method, a medium and a product. The near-memory DMA data transposition controller is arranged on a data transmission path between a far-end memory and a near-end memory of an AI computing chip, and comprises a first DMA control module and a second DMA control module. The transposition operation only occurs after data is read from the near-end memory, thereby reducing independent transposition processing links, reducing transposition power consumption overhead and operation delay, avoiding a decrease in bus bandwidth utilization caused by transposition, and reducing hardware resource overhead. A dynamic splitting strategy concentrates non-aligned access in a first data block, thereby improving overall bandwidth utilization. The transposition operation is separated from a computing unit, the transposition is completed synchronously in a data carrying process, computing resources are released, and an operation period and power consumption overhead are reduced.

This invention relates to the field of integrated circuits and discloses a mixed-precision in-memory computing circuit, data processing method, and chip. The invention includes: a storage array, an index memory, and a multiply-accumulate calculation circuit. The storage array includes a first data element stored in a first precision format and / or a second data element stored in a second precision format; wherein the bit width of the first precision format is greater than that of the second precision format; the storage locations of the storage array are divided according to the bit width of the second precision format; the first data element occupies multiple consecutive storage locations; the read bit width of the storage array is an integer multiple of the bit width of the first precision format; the index memory stores the position index information of the first data element in the storage array; the multiply-accumulate calculation circuit is used to determine the precision format corresponding to the data read from the storage array based on the position index information, and performs a multiply-accumulate operation corresponding to the precision format, outputting the calculation result. This solves the compatibility problem between mixed-precision data storage and computing circuits.

The present application provides a matrix multiplication operation circuit and method, the circuit comprising: an IO core, a memory connected to the IO core and storing target matrix data to be calculated, and multiple AI computing cores connected to the IO core and deployed together with the IO core on a target chip; the IO core comprises a matrix multiplication real-time block module, the matrix multiplication real-time block module determines the optimal block strategy based on the calculation task information of the target matrix data and the current chip parameter information when the target chip is running, and determines the block task information of each AI computing core according to the optimal block strategy and the weights corresponding to the multiple AI computing cores; the AI ​​computing core obtains the matrix block data based on the block task information and outputs the local calculation results through calculation; the local calculation results output by the multiple AI computing cores are combined into a matrix multiplication result. The present application can effectively improve the operation efficiency of the matrix multiplication operation and solve the limitations of the offline static matrix block strategy.

This application belongs to the interdisciplinary fields of semiconductor optoelectronic devices, multiferroic materials, and neuromorphic computing. Specifically, it discloses an in-situ differential optoelectronic synaptic device and its in-memory computing method. The method involves grounding the first and second electrodes, applying a voltage to the bottom electrode to change the polarization direction of the ferroelectric domains in the bismuth ferrite thin film, and using the polarization direction of the ferroelectric domains as the weight symbol in the neural weights to set the non-volatile synaptic weights. The voltage on the bottom electrode is then removed or reduced, and a light spot is used to illuminate the bismuth ferrite thin film. By adjusting the position of the light spot, the differential current between the first and second electrodes is read and used as the weight value in the neural weights, thus realizing the read operation. This application achieves integrated storage and computing.

The application provides a kind of spaceborne super high speed image intelligent processing method and device, including: high speed data interface unit, intelligent image processing unit, main control unit;The high speed data interface unit is connected respectively external data input unit, intelligent image processing unit and main control unit.This application keeps original data on front end FPGA, GPU module is only used as the position calculation of slice, avoids the repeated transmission of internal mass data, so as to cause the pressure of transmission bandwidth.

The invention discloses an asynchronous normal form-based simulation, storage and calculation integrated array control device, which comprises an asynchronous loopback handshake module for generating an asynchronous clock according to an operation result of a simulation, storage and calculation integrated array, a pre-stage circuit instruction and a state signal of a finite-state machine control module, handshake communication between the asynchronous loopback handshake module and the digital-to-analog converter is controlled through the asynchronous clock; and the finite-state machine control module is used for generating a gating signal according to the number of handshake communication times and sending the gating signal and an asynchronous clock to the gating module, and the gating module controls the analog storage and calculation integrated array through the gating signal and the asynchronous clock. According to the asynchronous normal form-based control device for the analog storage and calculation integrated array, the accurate transmission of data in a system unit is ensured, the data processing intensity and operation efficiency are improved, the circuit design and time delay are optimized, the charge loss is reduced, and the energy efficiency ratio of the whole architecture is improved.

The present invention discloses an area-saving cordic implementation method, which belongs to the technical field of on-chip system design. The cordic implementation method uses N to represent the preset number of Cordic iterations. When the number of iterations i does not reach N, and the judgment value d of the iteration direction is i When it returns to 0, it means that the calculation ends prematurely. At this time, the error value is introduced to force Cordic to return to 0 and enter forward rotation. After the number of iterations reaches N, the calculation is stopped. The coefficient K c or K h will become a constant, and finally the Nth iteration value and K c or K h The present invention introduces a minimum error of 1 LSB according to the selected system function and working mode, prolongs the number of iterations, makes the coefficient compensation value a constant, avoids the use of multipliers, and greatly saves chip area and power consumption.

The invention discloses a dynamic identification and prediction method based on photoconductive self-modulation, and belongs to the technical field of intelligent identification. According to the invention, a selenium vacancy defect is introduced into a high-mobility layered two-dimensional semiconductor bismuth oxide selenium, so that the selenium vacancy defect is separated from a conductive channel bismuth oxide layer, and a self-modulation photoelectric detector of ionic defect self-modulation channel electron transmission is realized; a device array formed by the self-modulation photoelectric detector is used as front-end signal processing hardware, continuously-changing external image information is continuously sampled and recorded, and back-end dynamic identification and prediction are carried out through a neural network of a software level. According to the invention, signal preprocessing is completed at an information input end by using a sensing, storing and computing integrated structure, so that the power consumption overhead of a hardware neural network is greatly reduced; and in combination with a subsequent network algorithm, small-area and low-cost mobile identification and prediction on a hardware level are realized.

The invention relates to the field of signal processing and the technical field of semiconductor integrated circuits, in particular to a storage and calculation integrated MIMO precoding circuit, a storage and calculation integrated MIMO precoding method, an operation framework and a communication system. Comprising two groups of novel memory arrays, an operational amplifier, a voltage phase inverter, a current phase inverter and a trans-impedance amplifier, the first novel memory array comprises a first sub-array, a second sub-array and a third sub-array, and the second novel memory array comprises a fourth sub-array and a fifth sub-array; the second sub-array is connected with the third sub-array through the voltage phase inverter, and the fifth sub-array is connected with the trans-impedance amplifier through the current phase inverter. The two novel memory arrays cooperatively work in the same analog calculation loop, so that the circuit directly outputs a pre-coding result in a steady state, and sampling hold, interface buffer and additional control logic required by cascade connection of multi-stage modules in the prior art are avoided, thereby reducing system time delay and power consumption overhead.

The invention discloses a single-capacitor temperature sensor based on duty ratio modulation of a BJT (Bipolar Junction Transistor), and belongs to the field of integrated circuits. The temperature sensor circuit respectively charges a capacitor with a positive temperature coefficient voltage and a negative temperature coefficient voltage in a cycle, two charging time periods are calculated, the time for charging the capacitor to the positive temperature coefficient voltage is divided by the sum of the two time periods, and the ratio is in direct proportion to the temperature, that is, the temperature is converted into a duty ratio to be output. Compared with a high-precision ADC quantization method, the power consumption and the circuit complexity can be greatly reduced. Besides, the circuit adopts a single-capacitor design, that is, two sections of charging processes are performed on the same capacitor, the sum (namely, cycle time) of the two sections of time can be irrelevant to the temperature only by designing a proper proportion of two sections of charging current, and the capacitor generally occupies most area of the whole chip, so that compared with a double-capacitor design, the area is greatly saved, and the cost is reduced. And errors caused by capacitor mismatch can be avoided.

The invention discloses a photoelectric detector based on a self-doping effect and application of the photoelectric detector as a dynamic neural network accelerator, and belongs to the technical field of high-performance sensing and sensing, storage and calculation integration. According to the photoelectric detector, layered two-dimensional semiconductor bismuth oxygen selenium is adopted as a channel layer, the position of a selenium vacancy is regulated and controlled through an interface acid etching method, the selenium vacancy is separated from an electron transport layer, the self-modulation effect of photoresponsivity is achieved, and wide-range photoresponsivity amplitude modulation and photoresponsivity change time constant modulation are achieved. The photoelectric detector is used as a dynamic on-chip optical neural network accelerator, can effectively perform dynamic weight adjustment, and is used for continuously changing object feature recognition, including object recognition and detection tasks under rotation, movement and degradation conditions.

The present disclosure discloses a computing apparatus configured to perform a binary operation on multi-dimensional data, a method for performing a binary operation by using a computing apparatus, and related products. The computing apparatus is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus respectively and is configured to store data of the computing apparatus and other processing apparatus. The disclosed scheme may reduce the number of data exchange and loading, relieve throughput pressure, and improve processing efficiency of a machine by rationally allocating the loading frequency of operation data.

The application discloses a reconfigurable digital in-memory computing device based on a multiplexed Booth computing unit and a 6T-SRAM. The device comprises 64 Booth multiplication in-memory computing processors. Each Booth multiplication in-memory computing processor comprises an in-memory computing array, and the in-memory computing array comprises a Booth multiplication in-memory computing data block, the Booth multiplication in-memory computing data block comprises an SRAM subarray and a Booth computing unit. The in-memory computing array has two working modes, namely a storage mode and a computing mode. In the storage mode, the in-memory computing array stores weight data input from outside. In the computing mode, the Booth multiplication in-memory computing processor outputs a 20-bit convolution computing result. The application supports configurable convolution computing scales, can flexibly cope with convolution neural network computing acceleration applications of different scales, improves the utilization rate of the in-memory computing array, and has the characteristics of high throughput and high energy efficiency.

The invention discloses an anti-radiation key circuit design method based on a magnetic random access memory, provides an anti-radiation standard unit reinforcement method of dual modular redundancy (DMR) for basic combinational logic units in a write drive circuit, a word line decoding / drive circuit and a column selection circuit, and establishes an anti-radiation standard unit library. The configuration of an anti-radiation unit library is completed around 15 standard units, a layout is drawn, and the data accuracy is simulated and verified at the same time. Compared with a traditional triple modular redundancy (TMR) reinforcement scheme, the method has the advantages that the power consumption, the layout area and the delay time are greatly reduced on the premise that the anti-radiation performance is maintained.

The invention provides a key path monitoring point screening method and system combining a path activation rate and similarity, and the method comprises the steps: obtaining the time sequence information of all paths of a target circuit based on static time sequence analysis, screening out the paths with the time sequence allowance smaller than a threshold value according to the preset time sequence allowance threshold value, and forming a key path set; on the basis of a preset benchmark test set, signal overturning statistics is conducted on monitoring points of all paths in the key path set, the activation rate of all the paths is calculated, the paths with the activation rate being zero are filtered out, and an effective path set is obtained; grouping the paths in the effective path set according to starting points of the paths to obtain a plurality of path groups; for each path group, calculating the similarity between the paths based on the logic topological structure sequence of the paths in the group, clustering the paths according to the similarity, and screening out at least one path from each cluster; and summarizing the paths obtained after screening of all the path groups to form a final monitoring point set.

This invention provides a low-noise amplifier and electronic device for a phased array system, relating to the field of antenna technology. The input common-gate transistor is connected to the output common-gate transistor via an inductor-coupled transformer. The inductor-coupled transformer increases the transconductance of both the input and output common-gate transistors by utilizing the mutual coupling of its multiple inductors and adjusting the coupling coefficients between pairs of inductors. As the radio frequency signal is amplified by the input and output common-gate transistors with increased transconductance, noise is reduced, and the signal is then output to the subsequent circuitry by the output common-gate transistor. This invention achieves increased transconductance of the dual transistors, reduced noise figure, increased circuit gain, excellent circuit performance, and simplified input and noise matching. It also improves system integration, reduces chip area and power consumption, and indirectly reduces the cost of radio frequency millimeter-wave phased array systems.

The invention discloses an instruction transmission processing device and an instruction transmission processing method of a sequential multi-transmission processor. The device comprises an instruction extraction unit, an instruction processing unit and a processing unit, wherein the instruction extraction unit is used for reading an instruction block from an instruction memory and pre-decoding the instruction block to form a transmittable instruction block; the instruction decoding module is used for decoding the instruction blocks received from the instruction extraction unit to obtain information of each instruction to be processed; the instruction emission validity arbitration module adopts a full associative storage structure and comprises a plurality of entries, and state information of an instruction is stored in each entry; the emission queue module is connected with the instruction emission validity arbitration module and is used for caching the to-be-emitted instruction passing arbitration; the execution unit is connected with the emission queue module and is used for executing the instruction and writing an execution result back to a corresponding entry of the instruction emission validity arbitration module; the hardware area is small, the processing efficiency is high, and pipeline pause can be avoided by distinguishing processing according to the type of the preorder instruction.

The application provides a transformer neural network acceleration device based on a photoelectric storage and calculation integrated device and a method thereof.The device comprises: (1) an encoding module comprising: a multi-head attention calculation submodule for performing a multi-head attention calculation operation on an input vector; a feedforward fully connected layer submodule for performing a fully connected operation and a linear rectification operation; an addition unit for adding the input vector and the output vector in the upper module; a normalization submodule for performing a normalization operation on the input vector from the addition unit; (2) a decoding module comprising: a multi-head attention calculation submodule, a feedforward fully connected layer submodule, an addition unit and a normalization submodule; (3) a classification prediction module for performing a fully connected operation on a one-dimensional vector output by the upper module and performing a classification output operation.The device of the application can accelerate the implementation of the transformer neural network and greatly reduce the power consumption, area and calculation delay of the hardware architecture.

The present application relates to the technical field of data processing, and more particularly to a rescue protective helmet data acquisition method based on multi-source sensing, which comprises the following steps: collecting a plurality of sensing data and a plurality of vital sign data in real time, and constructing a time neighborhood at the current time; calculating a safety correlation degree for any kind of sensing data at the current time; calculating a risk feature to obtain a cooperative risk degree according to the difference of the relative mean value and the change of the local slope relative to the overall slope of the sensing data within the time neighborhood, and combining the risk feature sequence correlation and the safety correlation degree difference to calculate an auxiliary risk reference degree; weighting and fusing the cooperative risk degree by using the auxiliary risk reference degree to obtain a safety risk index, and multiplying the safety risk index by the obtained safety core degree to obtain a safety criticality; and weighting and correcting the basic sampling frequency by using the safety criticality to obtain a dynamic sampling frequency. The present application realizes the cooperative scheduling of multi-source sensing data, and solves the problems of sampling redundancy and risk identification lag.

The invention discloses an SRAM (Static Random Access Memory)-based in-memory multiply-accumulate calculation device and method. The device comprises a first SRAM bit cell, a second SRAM bit cell, a first transmission gate circuit and a second transmission gate circuit, wherein the first transmission gate circuit comprises a first NMOS (N-channel Metal Oxide Semiconductor) tube, a first PMOS (P-channel Metal Oxide Semiconductor) tube and a first input port; the second transmission gate circuit comprises a second NMOS tube, a second PMOS tube and a second input port; a third MOS tube and a fourth MOS tube are arranged between the BLL bit line and the first and second transmission gate circuits; a fifth MOS tube and a sixth MOS tube are arranged between the BLR bit line and the first and second transmission gate circuits; a NOT gate is arranged between the BLR bit line and the carry output port, and the input end of the NOR gate is connected with the output end of the NOT gate and the BLL bit line. By adopting the technical scheme, multiply-accumulate results of two groups of inputs and weights can be directly output, a multiplication unit and a first-stage half adder circuit in an adder tree are not needed, the use of transistors is saved, the area and power consumption overhead of the adder tree are reduced, and the energy efficiency of the whole CIM macro is improved.