A test shell circuit and its design method

Abstract

The invention comprises: at least one test enclosure register chain used for testing the core to be tested; an interconnection circuit for connecting said test enclosure register chain to the core to be tested; an interconnection circuit for connecting said test enclosure register chain to the external data channel. The invention also reveals a method for designing the test enclosure circuit.

Description

technical field [0001] The invention relates to the technical field of testability design of integrated circuit chips, in particular to a test shell circuit designed for the bandwidth of an on-chip network data path and a design method thereof. Background technique [0002] Future SoCs will integrate hundreds or thousands of cores on a single chip made up of billions of transistors. Such a system-on-a-chip will require communication components with bandwidths of tens of gigabits per second, which must be reusable in order to meet time-to-market requirements. Many research works have proposed the use of switching networks as an alternative to interconnecting SoC cores. Such a network, known as a network-on-chip (NoC), addresses two key requirements for future systems: reusability and variable bandwidth. Many recent studies have shown that the network-on-chip will become the optimal solution for on-chip interconnection of system cores in the future. [0003] If the network ...

AI Technical Summary

Problems solved by technology

The network channel structure is designed and configured according to the operation of the network on chip in the working mode, so there may be a mismatch between the network channel bandwidth of a core logic and the number of core scan chains under test

This problem will not affect the test time of a single core, but the waste of network channels will bring additional network traffic, so it will have a huge impact on the total test time of the entire chip

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