Method and device for realizing data pre-fetching

Abstract

The invention provides a method and a device for realizing data pre-fetching. A pre-fetcher device comprises: a memory access mode recognition unit divides a global failure address flow into a local failure address flow, records information of two addresses with caching failure happening lately in the local failure address flow as history memory access information according to a time sequence, and captures a spanning memory access mode according to the record and generates a corresponding pre-fetching address. According to the invention, the storage utilization efficiency of a difference value related pre-fetcher is improved and the redundancy pre-fetching having no contribution to pre-fetcher performance improvement is reduced, so that the pre-fetcher can obtain a better performance optimization effect under the condition of same storage expense, and the cached bandwidth requirement and power consumption expense on a pre-fetcher access sheet are reduced effectively.

Description

technical field [0001] The invention relates to a method for optimizing the memory access performance of a modern microprocessor, in particular to a method and device for realizing data prefetching. Background technique [0002] With the progress of the integrated circuit manufacturing process, the performance of the processor and the memory is continuously improved. However, due to the difference in the production process and development route between the two, the performance improvement speed of the processor is significantly faster than that of the memory, so that the performance gap between the processor and the memory continues to increase. As a result, when the on-chip cache (On-Chip Cache) fails and the memory access instruction needs to access the main memory, the whole process often takes hundreds or even hundreds of clock cycles, forming a memory wall (Memory Wall) problem. [0003] Cache and memory hierarchy based on the principle of program access locality have ...

AI Technical Summary

Problems solved by technology

[0008] However, there is still a lot of room for optimization in the delta-associative prefetcher

On the one hand, the difference correlation prefetcher uses the global history buffer (GHB, Global History Buffer) of the circular queue structure to save all invalidation addresses that have recently occurred in cache failure in chronological order. For a stride memory access mode, although the previous one The invalidation address and stride value can be fully represented, but the delta-dependent prefetcher needs to use multiple global history buffer entries to store all invalidation addresses that have recently occurred cache invalidation in the stride access mode, so the storage utilization efficiency lower

On the other hand, the delta-dependent prefetcher will issue multiple prefetch requests according to the rules when it encounters a pattern match, and cannot judge whether the current prefetch address is a prefetched address, so a large number of redundant prefetch requests will be generated. fetches, wasting the bandwidth and power consumption of the processor accessing the on-chip cache

Images