26 results about "Cache invalidation" patented technology

The invention discloses a patch card state adaptive management method, which comprises the following steps of: actively scanning and constructing a detailed card slot information mapping table for persistent storage by pre-configuring an initialization flag bit when equipment is powered on for the first time; in the subsequent starting process, the cache information is directly read to skip a time-consuming physical discovery process, so that the starting efficiency is greatly improved. Meanwhile, a closed-loop self-repairing mechanism is built in the method, and by continuously monitoring the network registration state and verifying the data integrity, physical rescanning can be automatically triggered and the cache can be updated when cache failure or data errors are detected, so that the system can always return to the most reliable state acquisition mode.

Techniques related to performing remote cache failures are disclosed. In some embodiments, the main processor circuit is configured to transmit a cache failure command to the coprocessor circuit based on execution of a remote failure instruction (e.g., ISA-defined instructions). The coprocessor circuit includes a coprocessor cache circuit and a cache failure control circuit configured to control a cache failure command transmitted by the host processor in response to the cache failure command transmitted by the host processor. One or more cache lines in a coprocessor cache circuit are disabled without executing any instructions on the coprocessor circuit.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation to the format of the device emulation function, and 10 provide the translated cache invalidation function to the device emulation function being executed by a processor of the host device.

The invention relates to cache coherency. In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose the device emulation functionality to the host device; maintaining a peripheral equipment cache; invalidating a cache entry in the peripheral cache in response to receiving a cache invalidation from the back-end function; a conversion function is executed to convert between a format of the device emulation function and a format of the back-end function, receive a cache failure from the back-end function, convert the cache failure to the format of the device emulation function, and provide the converted cache failure function to the device emulation function being executed by the host device processor.

Rather than clearing out an entire address translation cache (ATC) upon receiving an invalidation request, a data storage device can focus on any individual untranslated addresses found in the invalidation request. The data storage device can, immediately upon receipt of the invalidation request, request translation of the untranslated address from a translation agent (TA). In response, the TA will provide a translated address. The data storage device can then compare translated addresses in the ATC to the translated address received from the TA. The data storage device can then complete any relevant commands associated with the untranslated address, flush the translated address and the untranslated address, and issue an invalidation completion. The total invalidation flow can be completed in less than 1 millisecond without clearing the entire ATC.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in the peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation into the format of the device emulation function, and provide the translated cache invalidation function to the device emulation function, which is executed by a processor of the host device.

The application relates to the technical field of artificial intelligence, and provides a cache control method and an artificial intelligence chip, the method comprising the following steps: determining the domain identification of a kernel; executing the kernel; in the execution process of the kernel, accessing the cache based on a memory access request, and storing the domain identification into the tag of the corresponding cache line in the cache; after the execution of the kernel is completed, controlling the cache to reset the tag of the cache line containing the domain identification in the tag. The cache control method and the artificial intelligence chip provided by the application realize kernel-granularity data isolation and guarantee data security. The tag resetting is limited to the cache line belonging to the kernel whose execution is completed, unnecessary cache invalidation operations are maximally reduced, the influence of memory access on the kernel being executed is reduced, the utilization rate of the cache is effectively improved, and the parallel processing performance of the artificial intelligence chip is guaranteed.

The invention discloses a high-performance password processing architecture and system based on multi-dimensional resource scheduling, and relates to the technical field of information security, the high-performance password processing architecture comprises a front-end management module, a password operation module and a main control module; according to the method, the working process is statically bound to the exclusive CPU core, cache failure and context switching overhead caused by cross-core scheduling are remarkably reduced, the competition bottleneck of a statistical module based on a lock mechanism under multi-thread concurrence is eliminated through the design of the lock-free atomic counter for cache alignment, and the service life of the statistical module is prolonged. Efficient updating of the counter is achieved through the atomic instruction, pseudo sharing and lock competition are avoided, transaction statistics can accurately feed back the system state in real time, and reliable data support is provided for scheduling decision making; meanwhile, by introducing a multi-listening socket technology, the performance limitation of a single-socket network model is broken through, and by configuring a plurality of listening sockets and optimizing buffer area and queue parameters, timely response and efficient processing of massive short connection requests are ensured.

An apparatus comprises invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation to the format of the device emulation function, and provide the translated cache invalidation function to the device emulation function being executed by a processor of the host device.

The present disclosure provides a data processing method, a retrieval method, an apparatus, a device and a storage medium, relates to the technical field of data processing, and in particular to the technical field of databases, information flows and knowledge graphs. The specific implementation scheme is: in response to receiving a construction instruction for an inverted index table corresponding to a forward index table, determining a target field value of a specified field in the forward index table; determining, based on the forward index table, to-be-indexed content corresponding to the target field value; constructing the inverted index table in a predetermined construction manner, taking the target field value as an index key and the to-be-indexed content as the key value of the index key; wherein the predetermined construction manner comprises: if the number of field values included in the to-be-indexed content does not exceed a predetermined number threshold, storing the to-be-indexed content in an array structure, otherwise storing the to-be-indexed content in a specified tree structure. It can be seen that, by the present scheme, the number of cache invalidations can be reduced and the data query speed can be ensured.

The invention discloses a method for improving client classification processing based on a cache technology, and belongs to the technical field of data processing. The method comprises the following steps: pre-importing index data and basic data in a database into a cache by using cache middleware and a local cache technology; in the large data volume analysis and calculation process, the access timeliness of the relational database is reduced, and the data response timeliness is improved. According to the method, through a caching technology, direct access to the relational database is reduced, and the data processing speed is remarkably increased; the load of the relational database is effectively reduced, and the overall performance of the system is improved; redis and Caffeine are used as cache layers, so that the increase of data volume and the extension of business can be better coped with; through a reasonable cache failure strategy and a data synchronization mechanism, the cache data is ensured to be consistent with the data in the relational database.

In some implementations, the techniques described herein relate to a method including: determining whether a distributed lock is available for an operation on a shared resource via a coordination server managing locks across a plurality of application servers in a multi-tenant environment; acquiring the distributed lock when available by generating a fencing token associated with the distributed lock, the fencing token being a monotonically increasing value managed by the coordination server; verifying the fencing token by a given application server prior to performing the operation on the shared resource; invalidating cached data across application servers after performing the operation, wherein cache invalidation is triggered by the given application server that performs the operation; and releasing the distributed lock to the coordination server after the operation, allowing other application servers to acquire the distributed lock.

The invention provides a dynamic rule processing method and device based on declarative configuration, a medium and a product, and relates to the technical field of rule engines, and the method comprises the following steps: constructing a rule object set in a memory by analyzing a declarative rule configuration file containing conditions, actions and cache strategies, a self-adaptive cache used for caching the handle is initialized; when a business object is processed, traversing rules according to a priority sequence, and acquiring and multiplexing a handle by utilizing a strategy-driven mechanism so as to efficiently execute condition judgment and action operation; the execution action judges whether the state of the current business object meets a cache failure triggering condition or not according to cache strategy information defined by a rule; and if yes, determining that the corresponding handle in the adaptive cache is invalid. By implementing the technical scheme provided by the invention, the data consistency and the result reliability in the dynamic rule processing process are ensured.

The invention provides a security transaction monitoring method, device and equipment and a storage medium, and the method comprises the steps: storing real-time market information data and a corresponding real-time timestamp through a first-stage cache, updating historical data in a second-stage cache according to the real-time timestamp and the real-time market information data in the first-stage cache, and storing the updated historical data in the second-stage cache; the historical data stored in the second-level cache is determined based on a cache failure strategy corresponding to a monitoring index set by a user, a multi-level cache structure is set, and the historical data is adaptively stored based on the set monitoring index, so that the dependence on a database is reduced, and the calculation efficiency is improved; and when a transaction instruction is received and the number of the monitoring indexes involved in the transaction instruction is multiple, generating a monitoring task corresponding to each monitoring index according to the updated historical data in the second-level cache and each monitoring index, executing the monitoring tasks in a parallel mode, determining a monitoring result of each monitoring task, and sending the monitoring result to the second-level cache. And the loop complexity is reduced, and the monitoring efficiency is improved.

This invention relates to the field of address translation cache invalidation technology, and in particular to a method and system for global invalidation of address translation cache based on generational flags. This invention maintains a current generational flag for each function identifier and records an entry generational flag for each address mapping entry. When a global invalidation request is received, only the current generational flag of the target function identifier is flipped, without traversing any address mapping entries. During a query, the entry generational flag is compared with the current generational flag of the function identifier: if they are not equal, the entry is marked as invalid and a re-request is triggered. Thus, global invalidation is reduced from traversing N entries to flipping only one flag bit, the time complexity is reduced from O(N) to O(1), eliminating performance jitter; the storage overhead is only a few KB, and the hardware implementation is simple; the comparison operation can be performed in parallel with the query step without increasing latency.

A system is provided for an improved cached STE invalidation. To track which STEs are updated, a memory is provided with a bitmap. Software identifies which STE are updated through the bitmap. Due to the update of the stored STE(s), corresponding STEs in a cache are stale. The software invalidates only the corresponding cached STEs as identified through the bitmap as opposed to invalidating all the cached STEs.

The application provides a consistency management method and device, electronic equipment, a storage medium and a product. The method comprises the following steps: in response to receiving a memory access instruction, obtaining a process identifier of a target process and a virtual address in the memory access instruction; determining a segment identifier corresponding to the virtual address; reading a corresponding first segment version number from a segment version register matrix of a memory management unit based on the process identifier and the segment identifier, and performing a retrieval operation on a translation lookaside buffer with the virtual address and the process identifier as indexes; in the case that a matching entry is retrieved, reading a stored second segment version number from the matching entry; in the case that the first segment version number is the same as the second segment version number, determining that the matching entry in the translation lookaside buffer is valid; in the case that the first segment version number is different from the second segment version number, determining that the matching entry in the translation lookaside buffer is invalid, thereby narrowing the invalid cache invalidation range and improving the cache hit rate of the translation lookaside buffer.

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Systems and methods for managing discontinuous access to an Integrated Digital Model Platform (IDMP) implements zero-trust and zero-knowledge security principles with client-side caching. Hie systems enable real-time data backup, efficient synchronization, and conflict resolution between local and cloud storage while maintaining data integrity and user control. An offline-first application supports intermittent connectivity environments, optimizing performance and security. Cache invalidation utilizes cryptographic techniques, including Elliptic Curve Diffie -Hellman, to create time-bound shared secrets between client and enclave for secure data encryption and session management. A token management system orchestrates data operations using fungible and non-fungible idempotent tokens for change detection across multiple tenant environments. The system coordinates between control plane and data plane components to ensure seamless user experience and data consistency during disconnected operations.

The invention belongs to the technical field of computer storage and data processing, and particularly relates to a data processing service method for memory cache optimization in a distributed storage system, which comprises the following steps of: constructing a peer-to-peer network based on consistent hash among a plurality of client nodes, and establishing a global metadata coordination service to manage data block metadata; metadata query is responded through a coordinator node, and data is directly migrated from other clients when the cache is missed; global popularity score calculation is introduced when a local cache elimination decision is made, and whether active migration is executed instead of direct elimination or not is judged in combination with a preset threshold value; and meanwhile, an exclusive lock and a cache failure broadcast mechanism of write operation are supported. Through the scheme, global collaborative management of cache resources can be realized, the cache hit rate is improved, the back-end storage access pressure is reduced, and the overall I / O performance of the system is remarkably enhanced.

The application discloses a Direct3D 12 view implementation method based on LOD state dynamic injection, and creates shared memory mapping containing a metadata area and a first cache area to a VKD3D user state when VK_EXT_image_view_min_lod is not supported, establishes third and fourth mappings and creates a sampler multiplexing pool after the VKD3D is started; intercepts and processes the creation of an SRV and a D3D12 sampler and the like, maintains cross-layer mapping and metadata, triggers cache invalidation; establishes mapping and binding context when the SRV is bound with the sampler, enhances the metadata hash carried by the descriptor set and the like, checks the metadata, recalculates the effective minLod and constructs injection commands to reconstruct and bind commands when submitting, and after the command buffer is submitted, the GPU executes the reconstructed command stream to realize the native D3D12 rendering effect.

The invention provides an optical flow processing method and device, electronic equipment and a storage medium, and relates to the technical field of image processing. The method comprises the steps of determining the position of a current image block in a to-be-processed image frame, determining the position of a next target image block based on spatial continuity when it is detected that the position is located at the edge of a processing line, taking the target image block as optical flow calculation input, and performing matching processing on the target image block and a reference image block in a cache line storage unit; and after the optical flow calculation of the current image block and the target image block at the edge position is completed, the remaining image blocks are continuously processed until the whole frame is completed. According to the scheme, cache failure caused by traditional line-by-line scanning can be avoided in the optical flow calculation process, so that the cache utilization rate and the data hit rate are improved, bandwidth occupation is reduced, and the stability and continuity of the calculation process are kept in the whole frame range.

The application is mechanical and electrical equipment fault diagnosis system and method based on knowledge graph, relates to mechanical and electrical equipment fault diagnosis technical field, and includes: atlas certainty partition module; memory continuity allocation module; boundary edge pruning index module; certainty multi-hop query execution module.In the application, the certainty coding mechanism based on the equipment physical bill of materials tree maps the physical hierarchical assembly relationship of the mechanical and electrical equipment into the binary semantic identification of nodes, and the continuous memory partition and linear storage layout are realized on the basis, the random memory access of the fault diagnosis is completely converted into sequential memory access, the processor hardware prefetch characteristics are fully adapted, and the occurrence probability of cache miss, page table cache invalidation and page fault interruption is reduced.

The application discloses a node-aware optimistic spin queue lock processing method and device. The method comprises the following steps: a current thread determines whether a corresponding NUMA node queue exists in a local NUMA node by searching a hash table; if the corresponding NUMA node queue exists, the current thread acquires an optimistic spin queue lock through the NUMA node queue; the current thread determines to release the optimistic spin queue lock; and the current thread calculates a probability parameter through a pseudo-random algorithm, and determines whether to transfer the optimistic spin queue lock in the local NUMA node or across NUMA nodes according to whether the probability parameter exceeds a preset value. The application has the following advantages: 1) reducing cache invalidation and high latency problems caused by cross-node memory access; 2) dynamically managing the queue through the hash table to avoid a sharp increase in memory occupation; 3) determining whether to transfer the lock to the local or across nodes through the pseudo-random algorithm; and 4) dynamically adjusting the probability of local and cross-node transmission to balance fairness and performance.