43 results about "Cache invalidation" patented technology

The invention provides a page table cache invalidation method, which is characterized in that a first data processing device in a first processing core sends invalidation operation information to a miscellaneous node, and the invalidation operation information at least comprises invalidation operation information which is not defined in an ARM instruction set and is defined in a non-ARM instruction set; the miscellaneous node notifies a second data processing device in the second processing core to execute a page table cache invalidation operation according to the invalidation operation information; according to the embodiment of the invention, the CHI protocol is expanded, page table cache invalid operation supported by the CHI protocol is supplemented, all-around TLBI operation can be supported, the CHI protocol and the instruction set adopted by the processing core are decoupled, the CHI protocol can be compatible with more instruction sets, the compatibility problem of a system on chip of a CPU (Central Processing Unit) containing a non-ARM instruction set can be solved, and the compatibility of the system on chip is improved. And the expansibility and the applicability are improved. The invention further provides a data processing device and a readable medium.

The invention discloses a patch card state adaptive management method, which comprises the following steps of: actively scanning and constructing a detailed card slot information mapping table for persistent storage by pre-configuring an initialization flag bit when equipment is powered on for the first time; in the subsequent starting process, the cache information is directly read to skip a time-consuming physical discovery process, so that the starting efficiency is greatly improved. Meanwhile, a closed-loop self-repairing mechanism is built in the method, and by continuously monitoring the network registration state and verifying the data integrity, physical rescanning can be automatically triggered and the cache can be updated when cache failure or data errors are detected, so that the system can always return to the most reliable state acquisition mode.

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

The invention discloses a data pre-reading method and device, a storage medium and electronic equipment, and relates to the technical field of file system data pre-fetching, and the method comprises the steps: obtaining response information corresponding to each read request after a file system responds to a plurality of read requests; under the condition that the response information indicates that cache failure exists in a first address responding to the read request, failure information corresponding to the first address is recorded, and the failure information at least comprises address data of the first address and offset information of a file stored on the first address; establishing a cache failure address table of the file system according to the failure information; and performing data pre-reading response on a target read request based on the cache failure address table, the target read request being a request executed after a plurality of read requests, and solving the problems of complex flow and low efficiency of data pre-reading in a complex I / O scene in related technologies.

Techniques related to performing remote cache failures are disclosed. In some embodiments, the main processor circuit is configured to transmit a cache failure command to the coprocessor circuit based on execution of a remote failure instruction (e.g., ISA-defined instructions). The coprocessor circuit includes a coprocessor cache circuit and a cache failure control circuit configured to control a cache failure command transmitted by the host processor in response to the cache failure command transmitted by the host processor. One or more cache lines in a coprocessor cache circuit are disabled without executing any instructions on the coprocessor circuit.

Provided in the present disclosure is a translation lookaside buffer invalidation method. The method comprises: a first data processing apparatus in a first processing core sending invalidation operation information to a miscellaneous node, wherein the invalidation operation information at least comprises invalidation operation information which has not been defined in an ARM instruction set and has been defined in a non-ARM instruction set, and the miscellaneous node notifies a second data processing apparatus in a second processing core to execute a translation lookaside buffer invalidation operation on the basis of the invalidation operation information. Further provided in the present disclosure are a data processing apparatus and a readable medium.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation to the format of the device emulation function, and 10 provide the translated cache invalidation function to the device emulation function being executed by a processor of the host device.

The invention relates to cache coherency. In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose the device emulation functionality to the host device; maintaining a peripheral equipment cache; invalidating a cache entry in the peripheral cache in response to receiving a cache invalidation from the back-end function; a conversion function is executed to convert between a format of the device emulation function and a format of the back-end function, receive a cache failure from the back-end function, convert the cache failure to the format of the device emulation function, and provide the converted cache failure function to the device emulation function being executed by the host device processor.

Apparatuses, methods, systems, and computer program products for sidecar cache invalidations and broadcasting is provided. A cache invalidation message may be received. The cache invalidation message may be published to a cache invalidation repository based on a region identifier of a plurality of region identifiers associated with the cache invalidation repository. A cache invalidation polling request may be received from a service associated with the region identifier. The cache invalidation message may be provided to the service associated with the region identifier.

The invention discloses an intelligent request preloading and cache failure control method and device, and the method comprises the steps: collecting the interaction behavior data of a user, synchronously obtaining the historical behavior data of a similar user group, generating real-time operation intention prediction through the interaction behavior data, generating group behavior trend prediction, and generating a resource request probability through dynamic weight fusion. The method comprises the following steps: calculating a resource loading priority by combining a real-time network state and an equipment load, triggering preloading of a high-priority resource in an idle period of a browser, setting a cache weight based on a request probability value, and actively triggering a cache failure when monitoring that the probability value is continuously lower than a set threshold value. And according to a matching result of the actual access behavior of the user and the preloaded resources, adjusting prediction model parameters in real time so as to optimize prediction precision. Through a dynamic weight prediction model fusing real-time interaction data and group historical behaviors and a cache intelligent elimination mechanism based on a probability threshold, the resource loading efficiency and the cache utilization rate are remarkably improved.

The invention discloses a PCIe (Peripheral Component Interconnect Express) cache consistency system implemented on a switch, which comprises the switch provided with a plurality of ports used for being connected with equipment; each port is provided with a port access table, the port access table is used for recording an event of establishing cache data with equipment corresponding to the port, and table items of the port access table comprise a BDF number, a physical address and a state flag; the consistency proxy unit is configured to carry out data modification on data in the table of all the port access tables; when the equipment performs write operation on external data or cached data, the consistency proxy unit establishes new table entries in the port access table of the equipment for storing the cached data and the port access table of the equipment from which the cached data comes; and modifying the table items which are different from the new table item in BDF number but the same as the new table item in physical address in other port access tables until the cache is invalid.

Rather than clearing out an entire address translation cache (ATC) upon receiving an invalidation request, a data storage device can focus on any individual untranslated addresses found in the invalidation request. The data storage device can, immediately upon receipt of the invalidation request, request translation of the untranslated address from a translation agent (TA). In response, the TA will provide a translated address. The data storage device can then compare translated addresses in the ATC to the translated address received from the TA. The data storage device can then complete any relevant commands associated with the untranslated address, flush the translated address and the untranslated address, and issue an invalidation completion. The total invalidation flow can be completed in less than 1 millisecond without clearing the entire ATC.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in the peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation into the format of the device emulation function, and provide the translated cache invalidation function to the device emulation function, which is executed by a processor of the host device.

The application relates to the technical field of artificial intelligence, and provides a cache control method and an artificial intelligence chip, the method comprising the following steps: determining the domain identification of a kernel; executing the kernel; in the execution process of the kernel, accessing the cache based on a memory access request, and storing the domain identification into the tag of the corresponding cache line in the cache; after the execution of the kernel is completed, controlling the cache to reset the tag of the cache line containing the domain identification in the tag. The cache control method and the artificial intelligence chip provided by the application realize kernel-granularity data isolation and guarantee data security. The tag resetting is limited to the cache line belonging to the kernel whose execution is completed, unnecessary cache invalidation operations are maximally reduced, the influence of memory access on the kernel being executed is reduced, the utilization rate of the cache is effectively improved, and the parallel processing performance of the artificial intelligence chip is guaranteed.

Cache invalidation circuitry responds to a cache invalidation command specifying invalidation scope information indicative of at least one invalidation condition, to control a cache to perform an invalidation process to invalidate cache entries satisfying the invalidation condition(s). Cache lookup circuitry issues to the cache a cache lookup request specifying address information, to request that the cache returns a cache lookup response. Cache lookup response filtering circuitry is responsive to a given hit-indicating cache lookup response which provides cached information and invalidation qualifying information returned from a corresponding valid cache entry, to determine whether the given hit-indicating cache lookup response conflicts with an in-progress cache invalidation command, based on the invalidation scope information specified by the in-progress cache invalidation command and the invalidation qualifying information, and when conflict is detected, causes the given hit-indicating cache lookup response to be treated as a miss-indicating cache lookup response.

The invention discloses a high-performance password processing architecture and system based on multi-dimensional resource scheduling, and relates to the technical field of information security, the high-performance password processing architecture comprises a front-end management module, a password operation module and a main control module; according to the method, the working process is statically bound to the exclusive CPU core, cache failure and context switching overhead caused by cross-core scheduling are remarkably reduced, the competition bottleneck of a statistical module based on a lock mechanism under multi-thread concurrence is eliminated through the design of the lock-free atomic counter for cache alignment, and the service life of the statistical module is prolonged. Efficient updating of the counter is achieved through the atomic instruction, pseudo sharing and lock competition are avoided, transaction statistics can accurately feed back the system state in real time, and reliable data support is provided for scheduling decision making; meanwhile, by introducing a multi-listening socket technology, the performance limitation of a single-socket network model is broken through, and by configuring a plurality of listening sockets and optimizing buffer area and queue parameters, timely response and efficient processing of massive short connection requests are ensured.

The application discloses a high-precision in-process memory access energy consumption calculation method, which comprises the following steps: S1, a CPU cache invalidation analyzer loads an executable file under Linux, filters CPU LLC cache invalidation access records of a process, and sends the CPU LLC cache invalidation access records to a message middleware; S2, a memory controller simulator reads the CPU LLC cache invalidation access records from the message middleware, outputs a memory controller access request sequence, and sends the memory controller access request sequence to the message middleware in real time; S3, a memory access instruction scheduler obtains the memory controller access request sequence from the message middleware, and converts the memory controller access request sequence into physical memory access instructions; and S4, a memory device energy consumption calculator calculates actual energy consumption of a memory device according to the physical memory access instructions. The application can help a process user to identify energy consumption hotspots and overall energy consumption levels of the process, and provides accurate basis for energy consumption optimization of the process.

The invention relates to the technical field of artificial intelligence, and provides a cache control method and an artificial intelligence chip, and the method comprises the steps: determining a domain identifier of a kernel; the kernel is executed, in the execution process of the kernel, the cache is accessed based on the memory access request, and the domain identifier is stored in a label of a cache line corresponding to the memory access request in the cache; and after kernel execution is finished, controlling the high-speed cache to carry out label resetting on the cache line containing the domain identifier in the label. According to the cache control method and the artificial intelligence chip provided by the invention, the data isolation of kernel granularity is realized, and the data security is ensured. Moreover, the tag is reset and limited in the range of the cache line belonging to the kernel of which the execution is finished, so that unnecessary cache failure operation is reduced to the maximum extent, the influence of memory access on the kernel which is being executed is reduced, the utilization rate of the cache is effectively improved, and the parallel processing performance of the artificial intelligence chip is further ensured.

An apparatus comprises invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry.

The application provides a cache data processing method and device and a storage medium, and the method comprises the following steps: a data operation interceptor acquires a database access statement in real time; if the execution of the database access statement causes a database change, a cache invalidation event is generated according to the database access statement, and the cache invalidation event is sent to a transaction-aware event scheduler; the transaction-aware event scheduler monitors a database transaction corresponding to the database access statement in real time, sends the cache invalidation event to an event broadcaster, and sends transaction execution information to the event broadcaster according to the execution result of the database transaction; the event broadcaster temporarily stores the cache invalidation event, and determines whether to send the cache invalidation event to an event processor according to the transaction execution information; after the event processor receives the cache invalidation event, the cache data is updated according to the cache invalidation event. The application can realize the decoupling of business logic and the cache mechanism, and ensure the consistency of database data and cache data.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation to the format of the device emulation function, and provide the translated cache invalidation function to the device emulation function being executed by a processor of the host device.

The present disclosure provides a data processing method, a retrieval method, an apparatus, a device and a storage medium, relates to the technical field of data processing, and in particular to the technical field of databases, information flows and knowledge graphs. The specific implementation scheme is: in response to receiving a construction instruction for an inverted index table corresponding to a forward index table, determining a target field value of a specified field in the forward index table; determining, based on the forward index table, to-be-indexed content corresponding to the target field value; constructing the inverted index table in a predetermined construction manner, taking the target field value as an index key and the to-be-indexed content as the key value of the index key; wherein the predetermined construction manner comprises: if the number of field values included in the to-be-indexed content does not exceed a predetermined number threshold, storing the to-be-indexed content in an array structure, otherwise storing the to-be-indexed content in a specified tree structure. It can be seen that, by the present scheme, the number of cache invalidations can be reduced and the data query speed can be ensured.

The embodiments of this specification disclose a multi-level caching method, device and medium for a distributed database, which relates to the field of database management technology and is used to solve the problem of poor dynamic collaborative management effect. The method includes: monitoring the configuration change events of the configuration center based on a long polling mechanism to obtain configuration update data; issuing the configuration rule parameters corresponding to the configuration update data to determine the current cache strategy, switching the cache level based on the current cache strategy, and realizing the caching of the current change data; monitoring the cache to determine whether the current microservice cluster has received a cache invalidation instruction; if so, receiving the operating indicators of the distributed relational database in real time to determine whether there is a database anomaly, so as to facilitate the retroactive update of the current cache strategy; based on the retroactively updated cache strategy, asynchronously synchronizing the current change data to the distributed cache database.

The invention discloses a method for improving client classification processing based on a cache technology, and belongs to the technical field of data processing. The method comprises the following steps: pre-importing index data and basic data in a database into a cache by using cache middleware and a local cache technology; in the large data volume analysis and calculation process, the access timeliness of the relational database is reduced, and the data response timeliness is improved. According to the method, through a caching technology, direct access to the relational database is reduced, and the data processing speed is remarkably increased; the load of the relational database is effectively reduced, and the overall performance of the system is improved; redis and Caffeine are used as cache layers, so that the increase of data volume and the extension of business can be better coped with; through a reasonable cache failure strategy and a data synchronization mechanism, the cache data is ensured to be consistent with the data in the relational database.

In some implementations, the techniques described herein relate to a method including: determining whether a distributed lock is available for an operation on a shared resource via a coordination server managing locks across a plurality of application servers in a multi-tenant environment; acquiring the distributed lock when available by generating a fencing token associated with the distributed lock, the fencing token being a monotonically increasing value managed by the coordination server; verifying the fencing token by a given application server prior to performing the operation on the shared resource; invalidating cached data across application servers after performing the operation, wherein cache invalidation is triggered by the given application server that performs the operation; and releasing the distributed lock to the coordination server after the operation, allowing other application servers to acquire the distributed lock.

One embodiment of a cache invalidation method includes storing an invalidation status usable by a computing node to identify, from a broadcast cache invalidation queue, a last processed invalidation that was processed with respect to an object cache used by the node. The method further comprises the node determining a set of unprocessed invalidations from the broadcast cache invalidation queue that are subsequent to the last processed invalidation determined from the invalidation status. The node processes the set of unprocessed invalidations to clear cached objects from the object cache. Based on processing the set of unprocessed invalidations to clear cached objects from the object cache, the invalidation status is updated with an identifier corresponding to a last invalidation from the set of previously unprocessed invalidations.

The invention provides a cache data processing method and device and a storage medium, and the method comprises the steps: a data operation interceptor obtains a database access statement in real time, and if the execution of the database access statement causes the database change, generates a cache failure event according to the database access statement, the cache failure event is sent to the transaction aware event scheduler, the transaction aware event scheduler monitors a database transaction corresponding to a database access statement in real time, sends the cache failure event to the event broadcaster, and sends transaction execution information to the event broadcaster according to an execution result of the database transaction; and the event broadcaster temporarily stores the cache failure event and determines whether to send the cache failure event to the event processor according to the transaction execution information, and the event processor performs cache data updating according to the cache failure event after receiving the cache failure event. According to the method and the device, decoupling of the business logic and the cache mechanism can be realized, and the consistency of the database data and the cache data is ensured.

An apparatus comprises invalidation range tracking circuitry to track at least one invalidation target address range specified as a target for cache invalidation; cache invalidation circuitry to request invalidation of cache entries corresponding to addresses in said at least one invalidation target address range tracked by the invalidation range tracking circuitry; and invalidate-write hazard detection circuitry to detect invalidate-write hazards based on a comparison of a write target address specified by a memory write request with the at least one invalidation target address range tracked by the invalidation range tracking circuitry.

The invention provides a dynamic rule processing method and device based on declarative configuration, a medium and a product, and relates to the technical field of rule engines, and the method comprises the following steps: constructing a rule object set in a memory by analyzing a declarative rule configuration file containing conditions, actions and cache strategies, a self-adaptive cache used for caching the handle is initialized; when a business object is processed, traversing rules according to a priority sequence, and acquiring and multiplexing a handle by utilizing a strategy-driven mechanism so as to efficiently execute condition judgment and action operation; the execution action judges whether the state of the current business object meets a cache failure triggering condition or not according to cache strategy information defined by a rule; and if yes, determining that the corresponding handle in the adaptive cache is invalid. By implementing the technical scheme provided by the invention, the data consistency and the result reliability in the dynamic rule processing process are ensured.