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Method and apparatus for increasing virtual storage capacity in on-demand storage systems

A method and apparatus are disclosed for increasing virtual storage capacity in on-demand storage systems. The method utilizes data compression to selectively compress data stored in a storage resource to reduce the utilization of physical storage space whenever such physical resources have been over committed and the demand for physical storage exceeds its availability. In one exemplary embodiment, the utilization of the capacity of a shared storage resource is monitored and data is selected for compression based on the utilization. The compression of the selected data is triggered in response to the monitoring results. In addition, policies and rules are defined that determine which data is selected for compression. For example, the selection of data may be based on one or more of the following: a degree of utilization of said capacity of said shared storage resource, a volume size of said data, an indicator of compressibility of said data, a frequency of use of said data, a manual selection of said data, and a predefined priority of said data. The disclosed methods improve the operation of virtual allocation by further enhancing the availability of physical space through data compression. Virtual allocation and block-based data compression techniques are utilized to improve storage efficiency with a minimal risk to system availability and reliability and with a minimal impact to performance (access time and latency).
Owner:IBM CORP

Transaction indentifier expansion circuitry and method of operation of such circuitry

ActiveUS20120290752A1Work wellSimple techniqueElectric digital data processingIdentifier ExtensionDeadlock
Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device. Reordering circuitry is then arranged to buffer response transfers received from the interconnect circuitry destined for the master device, with each response transfer having the revised transaction identifier associated therewith. The reordering circuitry then re-orders the response transfers having regard to the original transaction order of those transactions within the sequence of transactions that had the same initial transaction identifier, prior to provision of each response transfer to the master device. By such an approach, the performance of a high performance master device can be maintained, by ensuring that for at least the transactions targeted to a particular subset of the slave devices, no intervention by deadlock avoidance circuitry within the interconnect is required when routing transactions to those slave devices, due to the use of different transaction identifiers when accessing those slave devices.
Owner:ARM LTD
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