13 results about "Trace Cache" patented technology

The invention provides a multi-core processor cache coherence communication system based on FreeRTOS, and relates to the field of computer embedded systems, and the system comprises an application layer which comprises a plurality of tasks and is used for completing cross-core data interaction; the cache consistency communication layer is in communication connection with the application layer and the kernel layer; the cache consistency communication layer comprises a shared memory management module, a cache synchronization strategy scheduling module and a communication component synchronization adaptation module; the shared memory management module is used for tracking the cache state of the shared memory; the cache synchronization strategy scheduling module is used for selecting an optimal cache synchronization strategy according to the task and is linked with the task scheduler; the communication component synchronization adaptation module is used for identifying a corresponding shared memory block; the kernel layer comprises a memory manager, a task scheduler and a communication component; the communication component comprises queues, semaphores and event groups. According to the scheme, the problem of cache inconsistency is solved, and the correctness of cross-core data is ensured.

Disclosed embodiments relate to predicting when a fetch address will hit in a trace cache, e.g., to reduce power consumption when a hit is not predicted. In some embodiments, a processor caches instructions sequentially in a given cache line of instruction cache circuitry. The processor may identify traces of instructions that satisfy one or more criteria and store identified traces in a trace cache. The processor may predict whether a fetch address will hit in the trace cache circuitry. The processor may read in response to a prediction that the fetch address will not hit in the trace cache, instruction data from the instruction cache circuitry and not the trace cache circuitry for the fetch address. The processor may reduce power to (e.g., clock gate) portions of the trace cache circuitry in this scenario.

An apparatus and method for efficiently managing ray tracing to reduce cache contention are contemplated. In various implementations, a computing system includes a host processing circuit sending commands of a video graphics application to a parallel data processing circuit. The cache memory subsystem of the parallel data processing circuit stores copies of data used for ray tracing operations. A cache access monitor tracks cache access metrics such as cache misses, cache evictions, and cache access latencies of the cache memory subsystem. A control circuit controls a number of rays that can be sent to the ray tracing circuit from compute circuits of the parallel data processing circuit. The control circuit uses the monitored cache access metrics to reduce or increase the number of rays being processed or serviced at any given time.

The disclosed techniques relate to track caches. The switching logic for the track cache can identify tracks that meet one or more criteria. Generally, the internal branches of a track should meet a threshold for bias in a particular direction. To achieve this, the processor can initially assume that branches meet the threshold, track their usefulness within the context of the track over time, and prevent the inclusion of branches that fall below a usefulness threshold (indicating that these branches are not sufficiently biased). Branches that do not meet the threshold can, for example, be added to a Bloom filter. Usefulness can be tracked during track training, during validity in a track cache, or both.

The present disclosure relates to trace cache techniques based on bias control branch instructions. Trace cache circuitry configured to identify and cache traces that meet certain criteria. Prediction circuitry can track the direction of executed control branch instructions, including a first category of control branch instructions that meet a first threshold bias level towards a given direction (which can be referred to as "stable") and a second category of control branch instructions that do not meet the first threshold bias level (which can be referred to as "unstable"). The trace cache circuitry can identify traces of instructions that meet a set of criteria, including: only allowing control branch instructions of the first category as internal control branch instructions, and only allowing control branch instructions in the second category at the end of a given trace. Relative to certain conventional trace caches, the disclosed techniques can advantageously provide performance and power advantages of trace caching with reduced complexity.

Techniques can include: configuring stretched volumes to perform asynchronous replication in a first mode using a first replication technique that uses a write tracking cache to track locations that are written between successive replication-related snapshots of respective source volumes of the stretched volumes; performing asynchronous replication for the stretched volumes in accordance with the first replication technique; and monitoring resource consumption of the write tracking cache during asynchronous replication processing using the first replication technique, wherein said monitoring includes: determining that a current amount of write tracking cache consumed exceeds a high watermark threshold; and responsive to determining that the current amount of write tracking cache consumed exceeds a high watermark threshold, selecting, in accordance with criteria, one or more of the stretched volumes for demotion from the first replication mode to a second replication mode that uses a second replication technique that does not use the write tracking cache.

Disclosed techniques relate to branch prediction and trace caching. A processor may include trace cache circuitry configured to identify and store instruction traces that include multiple predicted-taken control transfer instructions. Prediction circuitry may include table circuitry configured to store a prediction table, CTI predictor lane circuitry having multiple lanes configured to access the prediction table to predict directions of multiple control transfer instructions in a given fetch group, and trace predictor lane circuitry configured to access the prediction table to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry. The prediction circuitry may, for a first control transfer instruction that is included in a trace as a non-terminating control transfer instruction, share a table entry in the prediction table and CTI predictor lane circuitry for both trace and non-trace predictions for the first control transfer instruction.

An apparatus and method for efficiently managing ray tracing to reduce cache contention are contemplated. In various implementations, a computing system includes a host processing circuit sending commands of a video graphics application to a parallel data processing circuit. The cache memory subsystem of the parallel data processing circuit stores copies of data used for ray tracing operations. A cache access monitor tracks cache access metrics such as cache misses, cache evictions, and cache access latencies of the cache memory subsystem. A control circuit controls a number of rays that can be sent to the ray tracing circuit from compute circuits of the parallel data processing circuit. The control circuit uses the monitored cache access metrics to reduce or increase the number of rays being processed or serviced at any given time.

Disclosed techniques relate to trace cache circuitry configured to identify and cache traces that satisfy certain criteria. Prediction circuitry may track directions of executed control transfer instructions, including a first category of control transfer instructions that meet a first threshold bias level toward a given direction (which may be referred to as “stable”) and a second category of control transfer instructions that do not meet the first threshold bias level (which may be referred to as “unstable”). Trace cache circuitry may identify traces of instructions that satisfy a set of criteria, including: only control transfer instructions of the first category are allowed as internal control transfer instructions and a control transfer instruction in the second category is allowed only at an end of a given trace. Disclosed techniques may advantageously provide performance and power advantages of trace caching with reduced complexity, relative to certain traditional trace caches.

Disclosed techniques relate to storing wide traces in a trace cache. In some embodiments, prediction circuitry predicts directions of control transfer instructions. Instruction cache circuitry may cache instructions sequentially in cache lines that store up to a first number of instructions. Trace cache circuitry may identify traces of instruction, store identified traces having up to the first number of instructions in first trace storage circuitry, and store identified traces having up to a second, greater number of instructions in second trace storage circuitry. This may advantageously allow longer traces to be executed from the second trace storage circuitry (without extensive changes to the instruction cache and processor front end, in some embodiments, due to the limited trace length for the first trace storage circuitry).

Disclosed are techniques for storing data decompressed from the compressed pages of a memory block when servicing data access request from a host device of a memory system to the compressed page data in which the memory block has been compressed into multiple compressed pages. A cache buffer may store the decompressed data for a few compressed pages to save decompression memory space. The memory system may keep track of the number of accesses to the decompressed data in the cache and the number of compressed pages that have been decompressed into the cache to calculate a metric associated with the frequency of access to the compressed pages within the memory block. If the metric does not exceed a threshold, additional compressed pages are decompressed into the cache. Otherwise, all the compressed pages within the memory block are decompressed into a separately allocated memory space to reduce data access latency.

The disclosed technology relates to a trace cache circuit configured to identify and cache traces that meet certain criteria. The predictive circuitry may track the direction of executed control transfer instructions, including a first category of control transfer instructions (which may be referred to as "stable") that comply with a first threshold bias level toward a given direction, and a second category of control transfer instructions (which may be referred to as "unstable") that do not comply with the first threshold bias level. The trace cache circuit may identify a trace of instructions that satisfy a set of criteria that include allowing only control transfer instructions of a first category as internal control transfer instructions, and allowing control transfer instructions in a second category only at the end of a given trace. The disclosed techniques may advantageously provide performance and power advantages of the tracking cache with reduced complexity relative to certain conventional tracking caches.

The disclosed technology relates to tracking a cache. The trace cache circuit may identify traces that meet one or more criteria. Typically, the inner part support of the tracking should meet a threshold offset level in a particular direction. To achieve this object, the processor may initially assume that branches meet a threshold, track their usefulness in the tracking context over time, and prevent branches below the usefulness threshold from being included (which indicates that those branches are not sufficiently biased). For example, branches that do not satisfy a threshold may be added to the Bloom filter. Usefulness may be tracked during trace training, when valid in a trace cache, or both.