14 results about "CPU cache" patented technology

The invention discloses a context-aware-based gap containerization TLS compatible method, which comprises the following steps of: distinguishing a simple TLS variable and a complex TLS variable in a source gap system, and establishing a TLS variable source feature; the method comprises the following steps: constructing a dynamic telescopic TLS memory pool matched with a variable access permission in a target system, expanding a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and a memory pool address, and optimizing and constructing a clustering structure aligned with a CPU cache line for a hotspot variable to improve the access efficiency; tLS variable access tracks are recorded through a dynamic binary translation engine, TLS segment descriptors are updated, the descriptors are read during thread switching to recover TLS context and refresh cache to guarantee consistency, address and offset conversion is completed according to target system alignment requirements by combining source features and a bidirectional mapping table for TLS variables of nested structures, pointers and array types, and the TLS variables of the nesting structures, the pointers and the array types are aligned. And completing dynamic conversion execution of the source system application program in the target system.

The application discloses a stability test method, device, equipment and storage medium of a DRAM particle. The method comprises the following steps: restarting a test system for a preset number of times, executing a preset test strategy in a universal boot loader stage of each test system starting process, the preset test strategy comprising the following steps: enabling a CPU cache, and configuring the CPU to access the DRAM particle in a non-burst transmission mode; based on hardware configuration information of the DRAM particle, allocating at least two test areas in an address space of the DRAM particle; traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particle in direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particle after the test system enters a sleep mode and wakes up under each working frequency. The application has the technical effect of providing sufficient test pressure by using the CPU cache and avoiding external interference after the system is completely started, and effectively improves the comprehensiveness and accuracy of the DRAM particle stability test.

In some examples, a method for regulating operations between a central processing unit (CPU) cache and a buffer of a memory module of a device includes the memory module placing a memory block including a plurality of cache lines for the device in a buffer of the memory module, the memory module querying the CPU cache for a plurality of modified cache lines associated with the memory block, and updating the plurality of cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the querying occurs prior to evicting the memory block from the buffer of the memory module of the device and / or writing back the memory block.

The application relates to a CPU performance test method and application under a Conda environment, belongs to the field of computer performance evaluation and optimization, and realizes comprehensive evaluation of CPU performance in combination with LAMMPS and LLCBench tools. The method quickly builds a test platform through the Conda environment, can evaluate the computing performance and parallel processing capability of the CPU by using LAMMPS, and can test the bandwidth and delay characteristics of CPU caches (L1, L2 and L3) through LLCBench. In combination with the two tools, the method realizes comprehensive testing of the computing performance and cache performance of the CPU, has the advantages of high efficiency, repeatability and wide application range, and provides scientific support for hardware performance evaluation and optimization.

The invention relates to the technical field of graph data processing, and provides a graph data processing method based on cache optimization, which comprises the following steps: constructing a cache optimization representation of graph data, and distributing a bit vector GT-vector with a fixed length of k for each vertex in a graph, each bit representing whether the vertex belongs to a pre-calculated maximum independent set; reserving adjacency list representation of the graph data, and storing the adjacency list representation as reference data in a memory; for an edge query request, reading GT-vectors of two vertexes from a CPU cache, and executing bit and operation; if the bit and the result are non-zero, judging that the edge is non-edge and immediately returning a first Boolean result indicating that the edge does not exist; and if the bit and result is zero, querying the adjacency list in the memory for verification, and returning a second Boolean result indicating that the edge exists or does not exist. According to the method and the device, the hybrid architecture combining the bit vector representation of cache optimization and the adjacency list is constructed, so that the magnitude order improvement of the graph data processing performance is realized on the premise of ensuring that the query result is completely accurate.

The invention discloses a stability test method and device for DRAM particles, equipment and a storage medium. The method comprises the steps that a test system is restarted for preset times, a preset test strategy is executed in the universal boot loader stage of each test system starting process, and the preset test strategy comprises the steps that CPU cache is started, and a CPU is configured to have access to DRAM particles in a burst transmission removing mode; based on the hardware configuration information of the DRAM particles, allocating at least two test areas in the address space of the DRAM particles; and traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particles during direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particles under each working frequency after the test system enters a sleep mode and is awakened. The DRAM particle stability testing method has the technical effects that the CPU cache is used for providing sufficient testing pressure, and the system is prevented from being interfered by the outside after being completely started, and the comprehensiveness and accuracy of the DRAM particle stability testing are effectively improved.

The application discloses a context-aware-based hyperjump containerized TLS compatible method, which comprises the following steps: distinguishing simple TLS variables and complex TLS variables in a source hyperjump system, and establishing TLS variable source features; constructing a dynamic scalable TLS memory pool matching variable access authority in a target system, extending a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and memory pool address, and optimizing hot spot variable to construct a cluster structure body aligned with CPU cache lines to improve access efficiency; recording a TLS variable access track through a dynamic binary translation engine, updating a TLS segment descriptor, reading the descriptor to recover a TLS context when thread switching, refreshing a cache to guarantee consistency, and converting addresses and offsets according to target system alignment requirements in combination with source features and the bidirectional mapping table for TLS variables of nested structures, pointers and array types, so as to complete dynamic conversion and execution of a source system application in the target system.

The invention relates to the technical field of data processing, in particular to a distributed real-time report generation method and system supporting incremental calculation. According to the invention, a real-time report system fusing distributed streaming computing, multi-version state management and column memory computing is constructed, an incremental computing model is taken as a core, and a real-time report is obtained through the steps of streaming data uptake and version state management, column memory storage and data structure optimization, and incremental computing and result combination. In combination with core modules such as streaming uptake, version allocation and a version state back end, only a data change part is processed, and low delay, high throughput and high resource utilization rate of a calculation process are realized. The report generation delay is reduced to the second level, the CPU cache hit rate and the resource utilization rate are improved, the framework has excellent expandability, and the system processing capacity can be linearly improved.

The invention provides a CPU cache allocation method and device, equipment, a storage medium and a program product. The method comprises the following steps: establishing a first instance set based on a received instance establishment request; and sending first information to a server, wherein the first information is used for instructing the first instance set to request CPU cache exclusive occupation and instructing a first cache needing to be allocated to the first instance set. According to the method, on-demand allocation of CPU caches can be realized according to actual conditions, and the processing capacity of tasks corresponding to instances is improved.

Provided in the present disclosure are a CPU cache allocation method, an apparatus, a device, a storage medium, and a program product. The method of the present disclosure comprises: on the basis of a received instance establishment request, establishing a first instance set; and sending first information to a server, the first information being used for indicating that the first instance set requests an exclusive CPU cache and indicating a first cache that needs to be allocated to the first instance set.

A system and method for due diligence optimization facilitates risk assessment in transactions by receiving subscriber health assessment data, extracting features via machine learning, and generating risk scores for matching buyers and sellers. The method employs a centralized platform with natural language processing and distributed ledger for secure data exchange. Enhancements include dynamic vector-guided depth-limited graph traversal for hierarchical question structures: generating query embeddings, retrieving node embeddings via HNSW indexing (M=16 links, ef_construction=200), computing cosine similarities, determining adaptive depth D using logarithmic formula based on relevance, pre-warming CPU cache, executing bounded traversal with lazy loading, and returning single-response results.

The invention discloses an NFS (Network File System) I / O (Input / Output) processing method based on an NUMA (Non Uniform Memory Access) architecture, which is characterized in that a corresponding configuration mechanism of a network port and a memory node is introduced under the NUMA architecture, so that an NFS server can identify a NODE to which a connection link belongs in a client mounting stage, and a working process is selected and awakened from a corresponding nfsd process pool based on the NODE attribute in an I / O request stage; therefore, the front-end network data and the rear-end processing thread are guaranteed to be located in the same NUMA node, localization of data processing and memory access is achieved, the problem of cross-node memory access caused by random scheduling of the nfsd process in the prior art is effectively avoided, high delay and bandwidth bottleneck caused by remote memory access are eliminated, and the service life of the NUMA node is prolonged. The I / O data is transmitted and copied in the same node, the I / O throughput rate and response speed of the NFS server in a high-concurrency scene are remarkably improved, and the CPU cache hit rate and the resource utilization rate are improved.

The invention relates to the technical field of path planning, and discloses a memory optimization method and system for path planning, terminal equipment and a storage medium, the memory optimization method for path planning comprises the following steps: pre-allocating a memory space with a fixed length as a storage queue, the storage queue being used for storing nodes to be explored and explored nodes during map path planning; determining a target node to be explored with the minimum total estimation cost in the storage queue; under the condition that the neighbor node of the target to-be-explored node is determined to be a new to-be-explored node, writing the new to-be-explored node into a storage queue; and accessing the storage queue again to obtain a next target node to be explored with the minimum total estimation cost until a termination node for map path planning is found. The node to be explored and the explored node are continuously stored in the memory, the effective utilization rate of the memory is improved, the memory requirement is reduced, and the CPU cache hit rate is improved.

The invention discloses a block chain edge computing scene-oriented post-quantum signature method based on NTT optimization, and relates to the technical field of block chains, and the post-quantum signature method is characterized in that on the basis of a lattice-based post-quantum signature algorithm, a three-level NTT optimization strategy is designed for edge node resource constraints, and the edge node resource constraints are optimized; the method specifically comprises the following steps of: initializing inertia NTT based on sparse polynomial pre-calculation; a stacked incomplete NTT step in a signature generation loop; and a rapid Barrett reduction and memory access optimization step under a fixed modulus. According to the method, repeated transformation of a matrix A is eliminated through inert initialization, the number of butterfly operations is reduced through stacked incomplete NTT, modular operation overhead is reduced through rapid Barrett reduction, signature generation is integrally accelerated, the requirement for real-time calculation is reduced through sparse pre-calculation, the CPU cache pressure is reduced through a memory access mode, and the real-time calculation efficiency is improved. Therefore, the overall memory bandwidth requirement of the system during the signature period is reduced, the method is more suitable for a low-end edge SOC, and the endurance time of battery-powered edge equipment is prolonged.