31 results about "CPU cache" patented technology

The invention discloses a context-aware-based gap containerization TLS compatible method, which comprises the following steps of: distinguishing a simple TLS variable and a complex TLS variable in a source gap system, and establishing a TLS variable source feature; the method comprises the following steps: constructing a dynamic telescopic TLS memory pool matched with a variable access permission in a target system, expanding a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and a memory pool address, and optimizing and constructing a clustering structure aligned with a CPU cache line for a hotspot variable to improve the access efficiency; tLS variable access tracks are recorded through a dynamic binary translation engine, TLS segment descriptors are updated, the descriptors are read during thread switching to recover TLS context and refresh cache to guarantee consistency, address and offset conversion is completed according to target system alignment requirements by combining source features and a bidirectional mapping table for TLS variables of nested structures, pointers and array types, and the TLS variables of the nesting structures, the pointers and the array types are aligned. And completing dynamic conversion execution of the source system application program in the target system.

A system and method for compressing regular data streams using instruction cache-resident perfect hash functions. The system employs machine learning to analyze regular data streams and generate optimized perfect hash functions that remain resident in CPU instruction cache during compression operations. Unlike traditional compression methods that store lookup tables in data cache, this approach transforms compression operations into executable instructions, enabling efficient processing while leaving data cache available for application data. The system comprises continuous monitoring of compression performance and data stream characteristics, automatically regenerating hash functions when significant changes are detected. The method encompasses analyzing data streams, generating hash function characteristics through machine learning, transforming these characteristics into optimized instructions, and deploying them in instruction cache for runtime compression operations. This approach improves compression performance for regular data streams by leveraging CPU cache hierarchy more efficiently than traditional lookup table-based methods.

The invention discloses a memory key value storage system thread scheduling method and device and a medium. According to the method, a system is organized into a two-layer architecture of a cache resident CR layer and a memory resident CR layer. Uniformly receiving and shunting all the requests by the CR layer; quickly processing the cached requests in the CR layer in a non-blocking manner; and the missed requests are forwarded to the MR layer in a non-blocking manner through the efficient communication queue. And after the MR layer processes the request, the completion signal is efficiently synchronized back to the CR layer by updating an implicit notification mechanism of the queue state identifier. According to the method, by effectively isolating tasks with different access characteristics, the CPU cache utilization rate is remarkably improved, load balance and low synchronization overhead under high concurrency are taken into account, and the overall performance and expandability of the system are improved.

The application discloses a stability test method, device, equipment and storage medium of a DRAM particle. The method comprises the following steps: restarting a test system for a preset number of times, executing a preset test strategy in a universal boot loader stage of each test system starting process, the preset test strategy comprising the following steps: enabling a CPU cache, and configuring the CPU to access the DRAM particle in a non-burst transmission mode; based on hardware configuration information of the DRAM particle, allocating at least two test areas in an address space of the DRAM particle; traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particle in direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particle after the test system enters a sleep mode and wakes up under each working frequency. The application has the technical effect of providing sufficient test pressure by using the CPU cache and avoiding external interference after the system is completely started, and effectively improves the comprehensiveness and accuracy of the DRAM particle stability test.

The present invention discloses a skip list structure based on persistent memory and an access method thereof, allocating persistent memory to the bottom-level linked list of the skip list, and persisting the bottom-level linked list of the skip list; designing a skip list structure optimized for CPU cache; inserting data into the skip list based on persistent memory; deleting data from the skip list based on persistent memory; and managing the free space of persistent memory. Through the present invention, when inserting, searching, and deleting operations are performed in the skip list based on persistent memory, the CPU cache and persistent memory hardware characteristics can be fully utilized, thereby improving the performance of the operation.

In some examples, a method for regulating operations between a central processing unit (CPU) cache and a buffer of a memory module of a device includes the memory module placing a memory block including a plurality of cache lines for the device in a buffer of the memory module, the memory module querying the CPU cache for a plurality of modified cache lines associated with the memory block, and updating the plurality of cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the querying occurs prior to evicting the memory block from the buffer of the memory module of the device and / or writing back the memory block.

In some examples, a method for regulating operations between a central processing unit, CPU, cache and a buffer of a memory module of an apparatus comprises placing, by the memory module, a memory block comprising multiple cache lines for the apparatus into the buffer of the memory module, querying, by the memory module, the CPU cache to obtain a plurality of modified cache lines associated with the memory block, and updating the multiple cache lines in the memory block based on the obtained plurality of modified cache lines, wherein the querying occurs before eviction and / or a write-back of the memory block from the buffer of the memory module of the apparatus.

The application relates to a CPU performance test method and application under a Conda environment, belongs to the field of computer performance evaluation and optimization, and realizes comprehensive evaluation of CPU performance in combination with LAMMPS and LLCBench tools. The method quickly builds a test platform through the Conda environment, can evaluate the computing performance and parallel processing capability of the CPU by using LAMMPS, and can test the bandwidth and delay characteristics of CPU caches (L1, L2 and L3) through LLCBench. In combination with the two tools, the method realizes comprehensive testing of the computing performance and cache performance of the CPU, has the advantages of high efficiency, repeatability and wide application range, and provides scientific support for hardware performance evaluation and optimization.

The disclosed computer-implemented method can include detecting, by at least one processor, a cache load from a second central processing unit (CPU) cache hierarchy onto an exclusively owned cache region of cache memory that is exclusively owned by a first CPU cache hierarchy. The method can additionally include converting, by the at least one processor, the exclusively owned cache region, in response to the detection, to a dual owner cache region at least in part by partitioning one or more fields of an entry for the dual owner cache region in a region-based probe filter. The method can also include employing, by the at least one processor, the entry for the dual owner cache region to track cache subregion subscriptions of both the first CPU cache hierarchy and the second CPU cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

The invention relates to the technical field of graph data processing, and provides a graph data processing method based on cache optimization, which comprises the following steps: constructing a cache optimization representation of graph data, and distributing a bit vector GT-vector with a fixed length of k for each vertex in a graph, each bit representing whether the vertex belongs to a pre-calculated maximum independent set; reserving adjacency list representation of the graph data, and storing the adjacency list representation as reference data in a memory; for an edge query request, reading GT-vectors of two vertexes from a CPU cache, and executing bit and operation; if the bit and the result are non-zero, judging that the edge is non-edge and immediately returning a first Boolean result indicating that the edge does not exist; and if the bit and result is zero, querying the adjacency list in the memory for verification, and returning a second Boolean result indicating that the edge exists or does not exist. According to the method and the device, the hybrid architecture combining the bit vector representation of cache optimization and the adjacency list is constructed, so that the magnitude order improvement of the graph data processing performance is realized on the premise of ensuring that the query result is completely accurate.

The invention relates to a CPU performance test method in a Conda environment and application, belongs to the field of computer performance evaluation and optimization, and realizes comprehensive evaluation of CPU performance by combining LAMMPS and LLCBench tools. According to the method, a test platform is quickly built through a Conda environment, and the computing performance and the parallel processing capacity of a CPU can be evaluated by using LAMMPS; the bandwidth and delay characteristics of caches (L1, L2 and L3) at all levels of the CPU can be tested through LLCBinch. By combining the two tools, the method realizes the comprehensive test of the computing performance and the cache performance of the CPU, has the advantages of high efficiency, repeatability and wide application range, and provides scientific support for hardware performance evaluation and optimization.

The invention belongs to the technical field of computers, and particularly discloses a persistent CPU (central processing unit) cache-based data-driven hash indexing method, which comprises the following steps of: constructing a directory-segment-bucket three-layer extensible hash structure in a persistent memory PM by adopting a DRAM-PM hybrid architecture, configuring a physical separation layout of metadata and key value pairs in a segment, storing the metadata in the head of the segment, and storing the metadata in the head of the segment; the key value pair is stored at the tail part of the segment; a plurality of round-robin queues are arranged in a DRAM, requests of index operation are collected and classified through the round-robin queues, a threshold value is set for each round-robin queue, when the data size in the round-robin queues reaches the threshold value, batch processing of data in the corresponding round-robin queues is triggered, and the batch processing is used for conducting batch persistence on the data to PM. According to the method and the device, the read-write amplification of the PM hash index can be effectively eliminated through the data layout optimization for the frequently accessed metadata and the CPU cache optimization for the scattered hash bucket access.

The application discloses a high-precision in-process memory access energy consumption calculation method, which comprises the following steps: S1, a CPU cache invalidation analyzer loads an executable file under Linux, filters CPU LLC cache invalidation access records of a process, and sends the CPU LLC cache invalidation access records to a message middleware; S2, a memory controller simulator reads the CPU LLC cache invalidation access records from the message middleware, outputs a memory controller access request sequence, and sends the memory controller access request sequence to the message middleware in real time; S3, a memory access instruction scheduler obtains the memory controller access request sequence from the message middleware, and converts the memory controller access request sequence into physical memory access instructions; and S4, a memory device energy consumption calculator calculates actual energy consumption of a memory device according to the physical memory access instructions. The application can help a process user to identify energy consumption hotspots and overall energy consumption levels of the process, and provides accurate basis for energy consumption optimization of the process.

The invention discloses a stability test method and device for DRAM particles, equipment and a storage medium. The method comprises the steps that a test system is restarted for preset times, a preset test strategy is executed in the universal boot loader stage of each test system starting process, and the preset test strategy comprises the steps that CPU cache is started, and a CPU is configured to have access to DRAM particles in a burst transmission removing mode; based on the hardware configuration information of the DRAM particles, allocating at least two test areas in the address space of the DRAM particles; and traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particles during direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particles under each working frequency after the test system enters a sleep mode and is awakened. The DRAM particle stability testing method has the technical effects that the CPU cache is used for providing sufficient testing pressure, and the system is prevented from being interfered by the outside after being completely started, and the comprehensiveness and accuracy of the DRAM particle stability testing are effectively improved.

The application belongs to the technical field of computers and specifically discloses a data-driven hash index method based on a persistent CPU cache, which comprises the following steps: a DRAM-PM hybrid architecture is adopted, a three-layer scalable hash structure of directory-segment-bucket is constructed in a persistent memory PM, and a physical separation layout of metadata and key-value pairs is configured in a segment, the metadata is stored in a segment header, and the key-value pairs are stored in a segment tail; a plurality of circular queues are set in DRAM, requests of index operations are collected and classified through the circular queues, a threshold is set for each circular queue, when the data volume in the circular queue reaches the threshold, batch processing of data in the corresponding circular queue is triggered, and the batch processing is used for batch persisting the data to the PM. Through data layout optimization of frequently accessed metadata and CPU cache optimization for scattered hash bucket access, the read-write amplification of the PM hash index can be effectively eliminated.

In some examples, a method for regulating operations between a central processing unit (CPU) cache and a memory module of an apparatus, the memory module comprising a plurality of memory blocks, comprises determining, by the CPU cache, a plurality of cache lines associated with the same memory block of the plurality of memory blocks, the plurality of cache lines stored in the CPU cache, and, in response to modifying a cache line of the plurality of cache lines associated with the same memory block, writing, by the CPU cache, the plurality of cache lines associated with the same memory block to the memory module.

Examples of computing systems that include I / O device(s) that respect an existing hardware resource partitioning in a modern computing platform are provided. The computing systems include at least one CPU having multiple cores and one or more CPU caches. The computing system also includes a main memory having locations, where each location maps to a set in the one or more CPU caches. A first subset of locations is partitioned for thread(s) of a first application and assigned to non-contiguous memory locations of the main memory. The computing system further includes an I / O device separate from the CPU that is configured to store I / O data in a second subset of locations that are different from the first subset of locations. The second subset of locations are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern.

The invention provides an inter-process communication method based on CPU (Central Processing Unit) cache, which comprises the following steps: a write-in control thread obtains the data volume of data to be transmitted, and batches the data to be transmitted by taking a preset single-batch transmission data volume A as a unit; the value of the single-batch transmission data volume A is smaller than the three-level cache capacity of the CPU; data are transmitted in batches by the following steps: a write-in control thread divides a single batch of data into a plurality of parts, and the parts are written into a shared memory in parallel by each channel write thread; temporarily storing the data in a three-level cache of the CPU at the moment of writing the data into the shared memory; each channel read thread reads the corresponding data and then stores the data in the local memory R, and after data transmission is completed, the receiving process reads the data in the local memory R to complete inter-process communication; according to the method, data is temporarily stored in a three-level cache of a CPU (Central Processing Unit) in a mode of transmitting the data in batches, and a receiving process directly reads the data in the three-level cache of the CPU; the data transmission is accelerated, and the inter-process communication speed is improved.

This invention specifically relates to a key-value separation storage method and system. This method and system uses an ART prefix tree as the basic data structure for data indexing. Within each data node, space is allocated separately for storing the key and value, and the corresponding SequenceNumber and ValueType are stored within the node, thus achieving key-value separation. No encoding is performed during data storage; the key, SequenceNumber, ValueType, and value are directly stored and retrieved. This reduces I / O throughput, increases CPU cache hit rate, and improves database read / write performance. Furthermore, this key-value separation storage method and system eliminates the need for decoding information during data read / write operations; information can be directly obtained using the node, reducing disk I / O consumption, lowering I / O throughput, increasing CPU cache hit rate, and improving database read / write performance.

The invention provides a high-performance tail-delay-controllable memory learning type index structure. The high-performance tail-delay-controllable memory learning type index structure comprises an internal index tree and a leaf node layer, an index entry of the internal index tree comprises a minimum key of a leaf node and a pointer pointing to the leaf node, and the space size of the internal index tree is adaptive to a CPU cache; the leaf node layer is composed of a plurality of leaf nodes, and each leaf node comprises a linear model, a Nano array and a Nano overflow array; each of the Nano array and the Nano overflow array comprises a plurality of Nano storage units, and the Nano array and the Nano overflow array form a plurality of groups; data keys are mapped to the Nano storage unit in the group in a Hash mode; the structure change operation of the leaf nodes is migrated in units of groups.

The application discloses a context-aware-based hyperjump containerized TLS compatible method, which comprises the following steps: distinguishing simple TLS variables and complex TLS variables in a source hyperjump system, and establishing TLS variable source features; constructing a dynamic scalable TLS memory pool matching variable access authority in a target system, extending a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and memory pool address, and optimizing hot spot variable to construct a cluster structure body aligned with CPU cache lines to improve access efficiency; recording a TLS variable access track through a dynamic binary translation engine, updating a TLS segment descriptor, reading the descriptor to recover a TLS context when thread switching, refreshing a cache to guarantee consistency, and converting addresses and offsets according to target system alignment requirements in combination with source features and the bidirectional mapping table for TLS variables of nested structures, pointers and array types, so as to complete dynamic conversion and execution of a source system application in the target system.

The invention relates to the technical field of data processing, in particular to a distributed real-time report generation method and system supporting incremental calculation. According to the invention, a real-time report system fusing distributed streaming computing, multi-version state management and column memory computing is constructed, an incremental computing model is taken as a core, and a real-time report is obtained through the steps of streaming data uptake and version state management, column memory storage and data structure optimization, and incremental computing and result combination. In combination with core modules such as streaming uptake, version allocation and a version state back end, only a data change part is processed, and low delay, high throughput and high resource utilization rate of a calculation process are realized. The report generation delay is reduced to the second level, the CPU cache hit rate and the resource utilization rate are improved, the framework has excellent expandability, and the system processing capacity can be linearly improved.

The invention provides a CPU cache allocation method and device, equipment, a storage medium and a program product. The method comprises the following steps: establishing a first instance set based on a received instance establishment request; and sending first information to a server, wherein the first information is used for instructing the first instance set to request CPU cache exclusive occupation and instructing a first cache needing to be allocated to the first instance set. According to the method, on-demand allocation of CPU caches can be realized according to actual conditions, and the processing capacity of tasks corresponding to instances is improved.

Provided in the present disclosure are a CPU cache allocation method, an apparatus, a device, a storage medium, and a program product. The method of the present disclosure comprises: on the basis of a received instance establishment request, establishing a first instance set; and sending first information to a server, the first information being used for indicating that the first instance set requests an exclusive CPU cache and indicating a first cache that needs to be allocated to the first instance set.

A high-performance, scalable hash index based on hybrid storage involves key-value storage and hash indexing. This index establishes a resizable collection log pool at the bottom level of the persistent CPU cache and flushes it to persistent memory in log units, bridging the gap between the key-value pair size and the write granularity of persistent memory. A smaller index is established in volatile memory to categorize the key-value pairs flushed from the collection logs. Seekless insertion and bottom-up search are used to eliminate pre-insert searches while ensuring correctness, reducing the read-write mix of insert operations. Checkless insertion results in multiple insertions of duplicate key values, so a low-overhead consistency check is added to the split to eliminate the index space occupied by duplicate keys. Large-capacity hash buckets are searched to increase the average number of probes. SIMD technology is used to store the characteristic values ​​of index keys in volatile memory, absorbing useless bucket probes in volatile memory and improving index search efficiency.

A system and method for due diligence optimization facilitates risk assessment in transactions by receiving subscriber health assessment data, extracting features via machine learning, and generating risk scores for matching buyers and sellers. The method employs a centralized platform with natural language processing and distributed ledger for secure data exchange. Enhancements include dynamic vector-guided depth-limited graph traversal for hierarchical question structures: generating query embeddings, retrieving node embeddings via HNSW indexing (M=16 links, ef_construction=200), computing cosine similarities, determining adaptive depth D using logarithmic formula based on relevance, pre-warming CPU cache, executing bounded traversal with lazy loading, and returning single-response results.

The invention discloses an NFS (Network File System) I / O (Input / Output) processing method based on an NUMA (Non Uniform Memory Access) architecture, which is characterized in that a corresponding configuration mechanism of a network port and a memory node is introduced under the NUMA architecture, so that an NFS server can identify a NODE to which a connection link belongs in a client mounting stage, and a working process is selected and awakened from a corresponding nfsd process pool based on the NODE attribute in an I / O request stage; therefore, the front-end network data and the rear-end processing thread are guaranteed to be located in the same NUMA node, localization of data processing and memory access is achieved, the problem of cross-node memory access caused by random scheduling of the nfsd process in the prior art is effectively avoided, high delay and bandwidth bottleneck caused by remote memory access are eliminated, and the service life of the NUMA node is prolonged. The I / O data is transmitted and copied in the same node, the I / O throughput rate and response speed of the NFS server in a high-concurrency scene are remarkably improved, and the CPU cache hit rate and the resource utilization rate are improved.

The invention relates to the technical field of path planning, and discloses a memory optimization method and system for path planning, terminal equipment and a storage medium, the memory optimization method for path planning comprises the following steps: pre-allocating a memory space with a fixed length as a storage queue, the storage queue being used for storing nodes to be explored and explored nodes during map path planning; determining a target node to be explored with the minimum total estimation cost in the storage queue; under the condition that the neighbor node of the target to-be-explored node is determined to be a new to-be-explored node, writing the new to-be-explored node into a storage queue; and accessing the storage queue again to obtain a next target node to be explored with the minimum total estimation cost until a termination node for map path planning is found. The node to be explored and the explored node are continuously stored in the memory, the effective utilization rate of the memory is improved, the memory requirement is reduced, and the CPU cache hit rate is improved.

The disclosed computer-implemented method can include detecting, by at least one processor, a cache load from a second central processing unit (CPU) cache hierarchy onto an exclusively owned cache region of cache memory that is exclusively owned by a first CPU cache hierarchy. The method can additionally include converting, by the at least one processor, the exclusively owned cache region, in response to the detection, to a dual owner cache region at least in part by partitioning one or more fields of an entry for the dual owner cache region in a region-based probe filter. The method can also include employing, by the at least one processor, the entry for the dual owner cache region to track cache subregion subscriptions of both the first CPU cache hierarchy and the second CPU cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses a block chain edge computing scene-oriented post-quantum signature method based on NTT optimization, and relates to the technical field of block chains, and the post-quantum signature method is characterized in that on the basis of a lattice-based post-quantum signature algorithm, a three-level NTT optimization strategy is designed for edge node resource constraints, and the edge node resource constraints are optimized; the method specifically comprises the following steps of: initializing inertia NTT based on sparse polynomial pre-calculation; a stacked incomplete NTT step in a signature generation loop; and a rapid Barrett reduction and memory access optimization step under a fixed modulus. According to the method, repeated transformation of a matrix A is eliminated through inert initialization, the number of butterfly operations is reduced through stacked incomplete NTT, modular operation overhead is reduced through rapid Barrett reduction, signature generation is integrally accelerated, the requirement for real-time calculation is reduced through sparse pre-calculation, the CPU cache pressure is reduced through a memory access mode, and the real-time calculation efficiency is improved. Therefore, the overall memory bandwidth requirement of the system during the signature period is reduced, the method is more suitable for a low-end edge SOC, and the endurance time of battery-powered edge equipment is prolonged.