72 results about "CPU cache" patented technology

A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the data pages are grouped by page-color, and then all the data pages of the weak locality dataset are scanned in a sequence of page-color grouping. Further, a number of memory pages having the same page-color are preset as a page-color queue, in which the page-color queue serves as a memory cache before a memory page is loaded into a CPU cache; the data page of the weak locality dataset first enters the page-color queue in an asynchronous mode, and is then loaded into the CPU cache to complete data processing. Accordingly, cache conflicts between datasets with different data locality strengths can be effectively reduced.

The invention discloses a virtual CPU scheduling method capable of enhancing real-time performance. The virtual CPU scheduling method comprises the following steps: a virtual machine management control tool accepts a command that a user operates a virtual machine and schedule parameters; the management control tool judges whether a user command is related with a real-time virtual machine, conditions for meeting schedulability of the real-time virtual machine are calculated if the user command is related with the real-time virtual machine, and physical CPU resources are dynamically partitioned according to the calculation result; scheduling is carried out by adopting the virtual CPU scheduling method capable of enhancing real-time performance, a global earliest deadline priority scheduling algorithm is applied to a CPU resource pool operating the real-time virtual machine, and a limit scheduling algorithm is applied to a CPU resource pool operating a non-real time virtual machine; optimization of virtual CPU caching and hitting is conducted on the global earliest deadline priority scheduling algorithm. According to the virtual CPU scheduling method capable of enhancing real-time performance, real-time performance of the real-time virtual machine is guaranteed, a good isolation property is provided for partitioning the CPU recourses, and influence on performance of the non-real time virtual machine is reduced.

The invention discloses a main memory database access optimization method on the basis of a page coloring technology. The method comprises the following steps of: firstly, carrying out sorting on an access sequence of all data pages of a weak locality dataset according to page colors and carrying out grouping on all the data pages according to the page colors; then scanning all the data pages of the weak locality dataset according to a sequence of grouping the page colors; furthermore, presetting a plurality of memory pages with the same page color into a page color queue, wherein the page color queue is used as a memory cache before the memory pages are uploaded into a CPU (Central Processing Unit) cache; and ensuring the data pages of the weak locality dataset to firstly enter the page color queue by an asynchronous mode and then be uploaded into the CPU cache to complete the data processing. The invention can solve the problem that in the main memory database application, a cache address space cannot be optimized and distributed for processes, threads or the datasets by the page colors, and effectively reduces cache conflicts between the datasets with different data locality intensities.

A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network. Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.

The invention discloses a multi-core CPU video transcoding scheduling method, which belongs to the field of video transcoding. Before a scheduling scheme is implemented, a static pressure test is carried out for a transcoding server in order to measure the maximum concurrent transcoding task number of a single CPU core; the scheduling scheme is started; the number of currently executed tasks of all the CPU cores is initialized as 0; if a new transcoding task arrives, then scheduling is carried out according to an allocation and scheduling method for new tasks; if a transcoding task is stopped, then scheduling is carried out according to an allocation and scheduling method for existing tasks; if a message for stopping all transcoding tasks is received, then a program is closed, and otherwise, the method rejudges whether a new transcoding task arrives, and carries out circular processing. The invention ensures that the transcoding tasks can be operated in the same CPU core to the greatest extent, thus effectively increasing the hit rate of the CPU cache and the operation efficiency of the system, and moreover, the loads of all the CPU cores can be balanced to the greatest extent.

The invention discloses a method for improving performance of multiprocess programs of application delivery communication platforms. The method includes hashing data packets to network card queues according to source IPs (internet protocols); binding the data packets in the network card queues to corresponding CPU (central processing unit) cores; binding the data packets received by the CPU cores with corresponding processes to process; respectively creating service programs for the processes, setting the service processes as REUSEPORT options, and binding IPs (internet protocols) and ports; running the corrected service programs, and adjusting the number of queues enabled by multi-queue network cards according to the number of the service processes; enabling each service process to be bond with one CUP core. By the method, hard interruption and soft interruption of the network cards can be balanced, CPU cores used for receiving and sending the data packets are the same, and thus, CPU cache hit ratio is increased.

An improved architectural approach for implementation of a microarchitecture for a low power, small footprint microcoded processor for use in packet switched networks in software defined radio MANeTs. A plurality of on-board CPU caches and a system of virtual memory allows the microprocessor to employ a much larger program size, up to 64k words or more, given the size and power footprint of the microprocessor.

The invention provides a method for controlling data transmission and a DMA controller. The method comprises the steps that configuration information of a CPU is received and analyzed, wherein the configuration information includes transmission width conversion parameters; data are read from a source peripheral and converted into the corresponding data width to be written in a target peripheral according to the transmission width conversion parameters. The transmission mode adopted for the DMA controller acts on direct exchange data between memories, between the memories and the peripherals and between the peripherals, CPU read-write commands are not executed, a CPU cache does not need to be used, and therefore intermediate links are reduced; only the DMA controller needs to be configured, all read-write time sequences are executed by hardware, and therefore the rate of data transmission is greatly increased.

Data access optimization features the innovative use of a writer-present flag when acquiring read-locks and write-locks. Setting a writer-present flag indicates that a writer desires to modify a particular data. This serves as an indicator to readers and writers waiting to acquire read-locks or write-locks not to acquire a lock, but rather to continue waiting (i.e., spinning) until the write-present flag is cleared. As opposed to conventional techniques in which readers and writers are not locked out until the writer acquires the write-lock, the writer-present flag locks out other readers and writers once a writer begins waiting for a write-lock (that is, sets a writer-present flag). This feature allows a write-lock method to acquire a write-lock without having to contend with waiting readers and writers trying to obtain read-locks and write-locks, such as when using conventional spinlock implementations.

The invention relates to a data search method. Data is organized and stored according to the fractal tree principle. The data search method includes: by a CPU, receiving a data reading request; searching the requested data in Cache Line; if the requested data is found in the Cache Line, reading the data and terminating the searching; if the requested is not found in the Cache Line, determining the possible storage position of the data in CPU Cache through numeric comparison; searching for the data in the corresponding interval in the CPU Cache according to the possible storage position of the data in the CPU Cache; if the requested data is found in the CPU Cache, reading the data and terminating the searching; if the requested data is not found in the CPU Cache, determining the possible storage position of the data in an internal memory; searching for the data in the corresponding interval in the internal memory according to the possible storage position of the data in the internal memory; if the requested data is found in the internal memory, reading the data and terminating the searching; if the requested data is not found in the internal memory, searching the data in a hard disk. By the data search method, the times of data exchanging between the Cache and the internal memory can be reduced, and CPU speed can be increased.

Provided are a system, method and medium for implementing cache consistency of a PCIe device, the system comprising: a CPU cache master controller configured to send a first read-write request of a CPU for a first address to a memory cache slave controller through a cache command of an internal bus; the memory cache slave controller is configured to update the state of the memory cache line of the first address according to the state of the memory cache line of the first address of the first read-write request, and send the first address and a command for updating the state of the cache line of the PCIe equipment to be the first state to the input/output bridge controller through a cache command of an internal bus; the input/output bridge controller is configured to send the first address and a command for updating the state of the cache line of the PCIe equipment to be in a first state to the PCIe equipment through a first PCIe bus message, receive first data from the first address of the PCIe equipment through a second PCIe bus message and receive a response for updating the state of the cache line of the PCIe equipment to be in the first state, and the cache command of the internal bus is sent to the memory cache slave controller.

The invention discloses a CPU which comprises a CPU body and further comprises: a second processor interconnection interface detachably connected with a first processor interconnection interface of the CPU body, a bus protocol module which is connected with the second processor interconnection interface and used for providing a bus protocol, a cache read-write control module which is connected with the bus protocol module and used for controlling read-write operation; and a cache memory which is connected with the cache read-write control module and is used for caching data information. According to the CPU provided by the invention, the cache space can be increased or reduced according to actual requirements, and the cache space of the CPU can be conveniently and flexibly adjusted, so that on one hand, the hit rate of the cache space of the CPU can be improved, the working efficiency of the CPU is further improved, and the system performance is improved; and on the other hand, waste of the cache space can be avoided. The invention also discloses an electronic device and a CPU cache control method, which have the above beneficial effects.

The invention particularly relates to a Key-value separated storage method and a Key-value separated storage system. According to the Key-value separation storage method and system, an ART prefix tree is used as a basic data structure of a data index, spaces are distributed for a key value and a value value in a node Node of each piece of data for storage, corresponding Sequence Number and Value Type are stored in the node Node, separation of Key-value is achieved, coding is not carried out any more in the data storage process, the key, the Sequence Number, the Value Type and the value are directly stored and read, and the data storage efficiency is improved. And therefore, the IO throughput is reduced, the CPU cache hit rate is increased, and the read-write performance of the database is improved. According to the Key-value separated storage method and system, corresponding information does not need to be decoded during data read-write operation, and the information can be obtained by directly using the node Node, so that the I/O consumption of a disk is reduced, the IO throughput is reduced, the CPU cache hit rate is increased, and the read-write performance of a database is improved.