174 results about "Software execution" patented technology

The invention discloses a multi-agent computer-aided engineering and a computer-aided design method. CAE simulation and design optimization for the design of a complex product are high in threshold and difficulty. According to the method, autonomous planning and automatic execution of CAE simulation and CAD design optimization tasks are realized by using a multi-agent technology based on a large language model. A user interacts with the multi-agent system in the modes of text input, voice, a graphical user interface and the like, the multi-agent system autonomously plans workflow steps according to the requirements of the user, all agents cooperatively execute the working steps in a labor division mode, CAE and CAD software is called to execute simulation and design change, CAE and CAD result data are read and analyzed, the task completion condition is evaluated, and the task completion condition is evaluated. And the task can be re-planned if necessary. The system can automatically process error information, and can notify a user to process when user intervention is needed. The performance of the system can be improved through fine tuning of a large language model and retrieval enhancement generation technology.

Methods and systems for detecting anomalous software behavior by monitoring frequency spectrums emanating from an electronic device are provided. A method includes storing frequency spectrum profiles for software applications and operational modes on the device. During execution of a software application, the real-time emanating frequency spectrum is measured and compared to the stored spectrum profile for that application and operational mode. Deviations between the real-time and reference spectrums indicate anomalous behavior from unknown software executing. The device determines a deviation exists and performs remedial actions like alerting the user, disconnecting from the network, shutting down, or switching application execution to another device. Frequency profiles are measured for new applications installed and stored to keep the data updated. Monitoring real-time frequency spectrums emanating from a device provides a computationally lightweight technique for detecting malicious software behavior without requiring complex analysis of application code.

The invention relates to the technical field of information security protection, and discloses a user real-name information protection method and system for competition appointment software. The method comprises the following steps: firstly, obtaining real-name information such as a user name, an identity card number and a contact way, and preprocessing to obtain desensitization preparation data; extracting sensitive features and determining distribution information, and combining a preset privacy constraint to generate an initial protection strategy; prediction feature distribution information and prediction use data are obtained through trend prediction, compensation optimization is carried out on the initial strategy according to the prediction feature distribution information and the prediction use data, and an optimization protection strategy is generated; after the strategy is applied, the protection effect is simulated and adjusted through reverse deduction to obtain a final protection strategy, and the final protection strategy is output to competition appointment software to be executed. According to the method, through multi-link processing and dynamic optimization, the real-name information security of the user is effectively protected, the data use requirements of each link of competition appointment are adapted, and the protection precision and flexibility are improved.

The invention discloses a power electronic dynamic system simulation model generation method, and belongs to the field of power electronics. Performing fine adjustment on the basic model to establish a simulation general large model; analyzing a simulation demand input by a user by utilizing the trained simulation large model, and generating a structured design intention map; inputting the structured design intention graph into the simulation large model, generating a simulation model basic instruction sequence or an execution code, and utilizing simulation model creation software to execute the instruction sequence or the execution code to create a simulation basic model; and carrying out automatic verification and iterative optimization on the simulation basic model by adjusting parameters, so that the simulation basic model outputs the capability of the simulation model with the optimal performance, and completing the generation of the power electronic dynamic system simulation model. Natural language driven modeling is achieved through the large simulation model, the technical threshold is lowered, the development period is shortened, the generated model can be directly integrated into a power electronic dynamic system simulation software environment, and the method is suitable for education, scientific research and industrial application.

Apparatuses, systems, and techniques to perform multi-threaded memory allocation in parallel by one or more software programs being performed on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, one or more software programs expressed in part by code using an application programming interface for parallel computing, such as CUDA, perform allocation, search, and deallocation of memory efficiently and in parallel on a GPU.

A method and a system for ensuring product quality in a process for producing a product from a material in a manufacturing plant via a software performed by a computer comprising the following steps of Establishing a data pipeline including a data transformation originated from different source systems, like an ERP, LIMS, or Data Historian, to the computer, wherein the data pipeline provides updated datasets to maintain up-to-date parameter information; Preparing the datasets for a multivariate analysis calculation and performing the multivariate analysis calculation via the software, wherein all relevant parameters, like quality parameter, process parameter, sub-suppliers' quality parameters, are included in the calculation; Visualizing the result data of the multivariate analysis calculation as a 2D plot on a display connected to the computer, wherein the software identifies and marks new production batches and reference batches, time series plots for the relevant parameters and principal components, and selected top parameters which contribute to a principal components' deviation from the new production batch; and Performing quality processes and workflows to improve the production process and product quality by using the visualized result data.

To efficiently and properly manage countermeasures against vulnerability of software, while considering software dependencies or responses to the vulnerability of constituent components.SOLUTION: A vulnerability countermeasure management system uses one or more information processing apparatuses including a processor and a storage apparatus. The system is configured to: acquire, as needed, configuration information of software applied to an execution environment of the software and vulnerability information which is information on vulnerability of constituent components of the software; detect vulnerability of the constituent components based on the vulnerability information; acquire information indicating dependencies between the constituent components of the software; determine countermeasures against the vulnerability of a first constituent component, which is one of the constituent components, in accordance with a status of measures against the vulnerability of a second constituent component, which is another constituent component dependent on the first constituent component; and generate information indicating the determined countermeasures.SELECTED DRAWING: Figure 2

This disclosure describes approaches for sandboxing a thread and memory resources within non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: providing a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to establish a sandbox for a particular thread that executes in the non-secure processing environment and is associated with at least one specified memory region; and associating other threads of the non-secure processing environment with the secure processing environment, such that the particular thread is unable to access memory resources of the other threads while the particular thread is sandboxed.

The invention relates to the technical field of software adaptation, in particular to a Beidou communication software development cross-platform adaptation method and system. The method comprises the following steps: defining an interface function library; constructing a virtual hardware logic module; linking the to-be-tested software, the interface function library and the virtual hardware logic module by utilizing a link rule, and determining an executable file of a single process; in the process of performing adaptation on the to-be-tested software by using the executable file of the single process, setting a simulation state of the virtual hardware logic module in response to calling of the state control interface by the test code, and setting a simulation state of the virtual hardware logic module in response to function calling of the native interface function by the to-be-tested software. And calling the virtual hardware logic module through an interface function library so as to carry out adaptation processing on the to-be-tested software. The invention aims to solve the problem that cross-platform adaptation cannot be realized due to the fact that all behavior characteristics of native hardware interfaces of different operating systems cannot be accurately reproduced in a virtual environment in the prior art.

The invention discloses a method and a device for checking updated software. A method and apparatus for verifying updated software may be associated with an infotainment platform of a vehicle. The software inspection method includes: receiving data for software inspection from an external server or an external device; generating a flow graph based on the received data; updating the flow graph based on the updated change specification of the software; reconfiguring the updated flow graph based on an estimated frequency of use of a display identifier ID added in an updated change specification of the software; and verifying the changed specification of the software by performing a test on the reconfigured flow graph, where the display ID is a unique identifier assigned to each displayable screen during the software execution process.

In some examples, a system monitors for a memory fault associated with execution of software. Based at least on receiving an indication of a possible memory fault, the system scans a first area of the memory based on a data structure that indicates that the first area of the memory stores a portion of parameters of the software that affect an accuracy of the software if there is a memory fault in the first area of the memory. Based at least on the scanning indicating that there is a memory fault in the first area of the memory, the system remaps the portion of parameters of the software from the first area to a second area of the memory that is determined to be free.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

The invention relates to the technical field of computers, and provides a synchronous task execution method and device, equipment and a medium, and the method comprises the steps: receiving a task queue set submitted by a plurality of user processes; obtaining a first execution task from a first task queue in the task queue set; under the condition that the first execution task is a synchronization task, simulating the first execution task based on a software language, and realizing a synchronization mechanism corresponding to the first execution task; and based on the synchronization mechanism and the scheduling rule, executing the execution task in the task queue set. The tasks in the task queues are scheduled through the synchronization mechanism corresponding to the software simulation synchronization task, so that the tasks are sequentially executed according to the expected sequence of the user process, the software executes the synchronization task, meanwhile, the task queues which do not meet the execution condition are switched in real time according to the scheduling rule in software simulation, and the execution efficiency is improved. And continuous waiting is avoided, and deadlock between the processes is further avoided when the multiple processes use the equipment at the same time.

The present invention relates to an apparatus and method for configuring a warp in a vector operation system. The apparatus includes: general-purpose registers; an arithmetic logic unit; a warp instruction scheduler; and a plurality of warp resource registers. The warp instruction scheduler allows each of a plurality of warps to include a part of relatively independent instructions in the program core according to the warp allocation instruction in the program core, and allows each of the plurality of warps to access all or specified local data in the general-purpose registers through the arithmetic logic unit according to the configuration during software execution, and completes the operations of each of the above warps through the arithmetic logic unit. The present invention can more widely adapt to different applications, such as big data, artificial intelligence operations, etc., through the above-described components that can allow software to dynamically adjust and configure general-purpose registers for different warps.

A method and apparatus for verifying updated software may be associated with an infotainment platform of a vehicle. The software verification method includes receiving data for software verification from an external server or external device, generating a flow map based on the received data, updating the flow map based on updated change specifications of software, reconfiguring the updated flow map based on estimated usage frequency of a display identifier (ID) added in the updated change specifications of the software, and verifying the changed specifications of the software by performing tests on the reconfigured flow map, where the display ID is a unique identifier assigned to each screen displayable during a software execution process.

The invention discloses a fault detection method and system based on reconstruction residual deep learning, and the method and system achieve the deep feature representation learning of the reconstruction residual of process data, thereby effectively mining the essence of hidden abnormal changes in the process data, and achieving the more effective and reliable fault detection. The fault detection method disclosed by the invention not only discloses a brand new deep learning architecture of the reconstructed residual deep learning model, but also discloses various structural improvement schemes related to each auto-encoder forming the reconstructed residual deep learning model, so as to better represent and learn deep features of the reconstructed residual; and the information comprehensiveness in the deep feature extraction process is improved from multiple angles. Besides, a fault detection system based on reconstruction residual deep learning is established through cooperation of hardware and software execution programs, and the fault detection system comprises a central control module, a data acquisition module, a display module and a fault alarm so as to execute the implementation process of the disclosed fault detection method.

The present application relates to the technical field of computer, and provides a synchronous task execution method, device, equipment and medium, the method comprises the following steps: receiving a task queue set submitted by multiple user processes; obtaining a first execution task from a first task queue in the task queue set; in the case that the first execution task is a synchronous task, simulating the first execution task based on a software language, realizing a synchronization mechanism corresponding to the first execution task; based on the synchronization mechanism and a scheduling rule, executing the execution tasks in the task queue set. The present application simulates the synchronization mechanism corresponding to the synchronous task by software to schedule the tasks in each task queue, so that each task is executed in turn according to the expected order of the user process, realizing the software to execute the synchronous task, and at the same time, the task queue that does not meet the execution condition is switched in real time according to the scheduling rule in the software simulation, avoiding waiting all the time, and further avoiding the deadlock between processes when multiple processes use the device simultaneously.

An in-vehicle device that is communicatively connected to multiple in-vehicle ECUs mounted on a vehicle, comprising a control unit that processes frames transmitted and received between the in-vehicle ECUs, the control unit acquires information about the software executed in each of the multiple in-vehicle ECUs, identifies the frames to be transmitted and received when the software is executed based on the acquired software information, identifies a transmitting ECU to transmit the identified frames and a receiving ECU to receive them, acquires frame definition information in the transmitting ECU and frame definition information in the receiving ECU, generates a frame conversion rule based on the frame definition information in the transmitting ECU and the frame definition information in the receiving ECU, converts the frames from the transmitting ECU using the generated frame conversion rule, and outputs the converted frames to the receiving ECU. [Effect] This device can provide an in-vehicle device that generates frame conversion rules.

A memory transaction may be tagged with a partition identifier selected based on which software execution environment caused the memory transaction to be issued. A memory system component may control allocation of resources used to process the memory transaction or manage contention for the resources based on a set of memory system component parameters selected based on the partition identifier specified by the memory transaction, or may control whether performance monitoring data is updated in response to the memory transaction based on the partition identifier specified by the memory transaction. A page table walk memory transaction may be assigned a partition identifier that is different from the partition identifier assigned to the corresponding data / instruction access memory transaction.

Apparatuses, systems, and techniques to perform multi-threaded processing in parallel by one or more software programs on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, processors, systems, and techniques, during execution of two or more software threads in parallel, identify, using at least one software thread of the two or more software threads, a child node of a parent node in a shared hierarchical data structure stored in memory as a candidate for a state-modifying operation, lock the parent node of the child node to indicate that an operation involving the child node is in progress, and perform, by the at least one software thread, a state-modifying operation on data associated with the child node when the parent node is locked.

The present invention is provided with: an aircraft having a control unit that executes airframe control, and a storage unit that stores software for executing the airframe control; and a simulator device for inputting input information pertaining to the airframe control to the aircraft and acquiring output information output from the aircraft. The aircraft executes software when simulation of the aircraft is executed. The storage unit stores actual aircraft data to which are imparted response characteristics pertaining to the airframe control corresponding to the input information. The control unit, when the aircraft simulation is executed, acquires input information from the simulator device, executes the airframe control by software on the basis of the acquired input information and the actual aircraft data, and outputs the control result of the airframe control as output information to the simulator device.

To aim at providing a system and program for generation allowed to appropriately conduct testing of software concerned.SOLUTION: A system for generation comprises a content, etc. acquiring means that acquires required-specification information indicative of a content of software concerned and written MBT-pattern definition information indicative of a MBT pattern as a criterion of a viewpoint of testing to be conducted on the software concerned and means for generation that generates a MBT model for conducting testing corresponding to the MBT pattern which the written MBT-pattern definition information indicates for the software concerned corresponding to the required-specification information, based on the required-specification information and written MBT-pattern definition information acquired by the content, etc. acquiring means. The generation means is to generate a MBT model corresponding to a state transition of the software concerned.SELECTED DRAWING: Figure 1

Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

To provide an information processing system and a program capable of recording an execution result of recovery processing of firmware of a functional device in a log.SOLUTION: When tampering of firmware of a functional device is detected in a state where controller software is started, information indicating execution of recovery processing via the controller software is recorded in a storage unit, installer software is started in a state where the controller software is not started, the recovery processing is executed via the installer software, and after the execution of the recovery processing, the controller software is started, and when the firmware of the functional device is normal and the information indicating the execution of the recovery processing is recorded in the storage unit, the execution of the recovery processing via the controller software and the success of the recovery processing are recorded in a log.SELECTED DRAWING: Figure 6

The invention discloses a closed source software system behavior description method based on virtualization, which comprises the following steps of: starting a VMX mode, and configuring a processor register to support a virtualization environment; a binary instruction stream of the closed source software is analyzed, and a real function entry address of the target is obtained; setting an INT3 breakpoint at the function entry address, and storing an original instruction; and breakpoint triggering information is received and processed through the Hypervisor layer. According to the method, the execution process of the closed source software is captured and analyzed in the virtual environment, the analysis process reduces the dependence on the symbol table, the system call sequence is modeled and analyzed in combination with the Markov chain model, the operation behavior of the closed source software is accurately described, and in addition, the operation efficiency of the closed source software is improved. According to the method, regular behaviors of normal applications can be found, and potential abnormal calling and malicious behaviors can be identified in time, so that a customization function is realized according to requirements, and a reliable basis is provided for system security monitoring and behavior analysis.

Provided is a communication device that executes packet processing through software processing and hardware processing. In order to suppress an increase in load on software processing in migration of packet processing, the communication device comprises: at least one packet processing unit which executes packet processing with software; and a packet processing circuit which executes packet processing with hardware, wherein, in all-at-once migration in which a system failure occurs, packet processing with a greater processing load is preferentially executed with the packet processing circuit.

During execution of software a processing unit issues asynchronous operations such that there are multiple asynchronous operations, such as memory operations, in flight (that is, pending execution completion) from a single set of instructions, such as a wavefront or warp. In some cases, the processing unit executes other operations while the multiple asynchronous operations are pending. Performance monitor circuitry records information, such as asynchronous operation count information, register file scoreboard information, and the like, that allows a software engineer to identify which of a plurality of asynchronous operations caused a stall.

Aspects of the disclosure include methods and systems for performing automated software testing using chaos engineering. An exemplary method can include obtaining a plurality of fault scenarios and executing a test script on software under test during application of each of the plurality of fault scenarios, wherein the test script simulates the execution of a function of the software under test. The method also includes recording, for each of the plurality of fault scenarios, telemetry data regarding the execution of the function of the software under test and identifying a vulnerability of the software under test based on the recorded telemetry data.

An on-board device includes a control unit performing processing relevant to a frame transmitted / received between the on-board ECUs, in which the control unit acquires information relevant to software executed in each of the plurality of on-board ECUs, specifies the frame transmitted / received when the software is executed, on the basis of the acquired information relevant to software, specifies a transmission ECU transmitting the specified frame and a reception ECU receiving the specified frame, acquires definition information of the frame of the transmission ECU, acquires definition information of the frame of the reception ECU, creates a conversion rule of the frame, on the basis of the definition information of the frame of the transmission ECU and the definition information of the frame of the reception ECU, converts the frame from the transmission ECU by using the created conversion rule of the frame, and outputs the converted frame to the reception ECU.

The present invention provides an off-line software-in-the-loop simulation development system and an off-line software-in-the-loop simulation method. A general firmware architecture is compiled to generate a chip control program. The general firmware architecture includes an application layer and a hardware abstraction layer. The application layer has a setup header file and a product program. Processing programs required by peripheral modules are added to the hardware abstraction layer at compile time. The chip control program is provided to a controller chip or circuit simulation software to control product-related circuits by controlling peripheral modules.