Method and system for protecting CPU Cache data after AC power failure

Abstract

The invention discloses a method for protecting CPU Cache data after AC power failure. The method comprises the steps that a CPLD sends a data protection command to a CPU after receiving AC power failure information; and the CPU flashes data in a CPU Cache to a non-volatile storage medium after receiving the data protection instruction, thereby performing a subsequent ADR process after finishing the flashing. According to the method provided by the invention, the data in the CPU Cache can be effectively protected after the AC power failure only by adding the process of flashing the data in theCPU Cache to the non-volatile storage medium after the AC power failure on the premise of not changing the read-write performance of the non-volatile storage medium, so that the data in the CPU Cacheis protected from being not lost, the read-write performance of NVDIMM-N or other non-volatile storage mediums is not influenced, and the delay is shortened. The invention furthermore discloses a system for protecting the CPU Cache data after the AC power failure. The system also has the abovementioned beneficial effects, which are no longer repeated here.

Description

technical field [0001] The invention relates to the field of storage technology, in particular to a method and system for protecting CPU Cache data after AC power failure. Background technique [0002] In the era of big data, the value of data is getting higher and higher. How to protect data from loss is a technical issue that technicians have been working hard to study. In many previous designs, the battery backup unit BBU is usually used for data protection after power failure, but the battery module in the BBU is usually bulky, requiring an additional increase in the size of the structure, and the charging time is long. Now NVDIMM-N, AEP (Apache Pass) and other non-volatile storage media are more and more popular. For example, for NVDIMM-N, after AC power failure, the system starts the ADR (Asynchronous DRAM Refresh) process, notifies the CPU of the AC power failure information, and the CPU refreshes the data in the ADR safe zone to DRAM, so that NVDIMM-N can rely on T...

AI Technical Summary

Problems solved by technology

[0003] However, according to the current Intel ADR function, the data in the ADR safe zone does not include the CPU Cache, so the data in the CPU Cache cannot be effectively protected after power failure, which leads us to use NVDIMM-N or other non-volatile storage Some measures need to be taken to avoid data loss in CPU Cache

The current solution is to change the write mode of the CPU to non-write-through mode, that is, the write data does not pass through the CPU Cache, and the write completion signal is returned after being written to the DRAM, so that although the data in the CPU Cache will not be lost after power failure, but It will increase the write delay; another method is to control the data in the CPU Cache to be written to the DRAM through Intel instructions and then return. Although this method can ensure that the data in the CPU Cache has been sent to the DRAM before power failure, And compared to the previous method, the delay will be smaller, but compared to the normal write-through mode, it will still increase the delay

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