10 results about "NVDIMM" patented technology

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

The invention discloses a dynamic hierarchical storage method and system based on a lake and warehouse integrated architecture, and relates to the technical field of dynamic hierarchical storage, and the dynamic hierarchical storage system comprises a data management layer which is based on a Catalog, Database and Table three-layer logic structure of Apache Dores; the physical storage layer comprises a cache layer, a middle buffer layer and a persistence layer; the cache layer is composed of an NVRAM / NVDIMM (Non-Volatile Random Access Memory / Non-Volatile Delivery Infrastructure Module) and is carried on a BE / FE node of Dores; the middle buffer layer is composed of a Burst Buffer system constructed by an NVMe SSD (Non-Volatile Memory Express Solid State Disk); the persistence layer comprises an SSD (Solid State Disk) array and a disk array and is used for low-cost and high-capacity data retention; and the calculation engine layer is used for integrating Satunnel, Spark and Flink. The technical problem to be solved by the invention is to provide the dynamic hierarchical storage method and system based on the lake and warehouse integrated architecture, and hierarchical storage and automatic migration of lake and warehouse data are realized through definition of hotspot data, label definition of structured data and unstructured data and data attributes by fusing common big data calculation engines such as seatunnel, Flink and Spark.

According to the power supply management system of the computing device and the computing device, when the second terminal voltage of the control module is lower than the set value, the output power supply of the power supply unit is abnormal, at the moment, the switching module is switched to the standby power supply for supplying power, and the CPU is controlled to enter the standby state; the standby power supply supplies power to the standby voltage regulator and the memory voltage regulator, the standby voltage regulator is used for providing power for maintaining the standby function of each module in the standby state, and the memory voltage regulator is used for providing power for maintaining the original functions of the memory module and the data storage related module in the standby state. According to the embodiment of the invention, the universal DIMM can be matched based on the CPU on the market, the memory data protection after the power failure of the computing equipment is realized, the CPU does not need to support the NVDIMM, the NVDIMM does not need to be matched, and the hardware cost is reduced.

The application discloses a kind of dynamic hierarchical storage method and system based on lake warehouse integrated architecture, it is related to dynamic hierarchical storage technical field, including: data management layer: based on Apache Doris's Catalog, Database and Table three-layer logical structure;Physical storage layer: including cache layer, intermediate buffer layer and persistent layer;The cache layer is made of NVRAM / NVDIMM, is carried on the BE / FE node of Doris;The intermediate buffer layer is made of the Burst Buffer system of NVMe SSD construction;The persistent layer includes SSD array and disk array, for low-cost large-capacity data retention;Computing engine layer: integration Seatunnel, Spark and Flink.The technical problem to be solved in the application is to provide a kind of dynamic hierarchical storage method and system based on lake warehouse integrated architecture, fusion big data commonly used computing engine such as seatunnel, Flink, Spark, through the definition of hot spot data, the label definition of structured data and unstructured data, and the hierarchical storage and automatic migration of lake warehouse data are realized by data attribute.

A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and / or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

The utility model discloses a domestic server supporting NVDIMM-N. The domestic server comprises a server mainboard arranged in a case, the server mainboard comprises a power supply, a CPLD (Complex Programmable Logic Device), a CPU (Central Processing Unit) module and a memory module, the power supply, the CPLD, the CPU module and the memory module are electrically connected in sequence, the memory module comprises a preset number of memory slots, and the memory slots are electrically connected with the CPLD. A plurality of memory slots are formed in the CPU module, an NVDIMM-N memory bank is inserted in each memory slot, the CPU module is electrically connected with each NVDIMM-N memory bank through a first bus, and the CPLD device is electrically connected with each NVDIMM-N memory bank. According to the domestic server supporting the NVDIMM-N, memory data storage under the abnormal power failure condition is achieved through the NVDIMM-N memory bank, and data are recovered from the NVDIMM-N after a mainboard is powered on again so as to be rapidly recovered to the state before power failure; according to the technical scheme, the super capacitor can be placed in the disk position of the front backboard on the premise of not increasing structural parts, compatible multiplexing of the disk position and the super capacitor position is achieved, and space is saved.

A method for operating a non-volatile dual in-line memory module (NVDIMM) is disclosed. The NVDIMM includes a dynamic random access memory (DRAM) and a non-volatile memory (NVM) device, the DRAM including a first input / output (I / O) port and a second I / O port, and the second I / O port connected to the NVM device. The method includes receiving an externally provided command signal representing a read / write command and a transfer mode, driving a multiplexer according to the transfer mode of the command signal to select at least one of the first I / O port and the second I / O port, and reading or writing data in at least one of the DRAM and the NVM device according to the read / write command of the command signal using the at least one of the first I / O port and the second I / O port selected by driving the multiplexer.

The invention discloses a persistent memory crash recovery method and system combining an operation queue and collaborative synchronization. The persistent memory crash recovery method and system are suitable for an Optan DCPMM or NVDIMM-based file system. According to the method, a file system is divided into a newest view and a consistent view, metadata packaging and scheduling are carried out by adopting an operation queue bound according to files, and asynchronous persistence is completed through foreground and background threads. The system dynamically monitors a plurality of indexes based on the FoF window, regulates and controls the check point period and the persistent batch of the operation nodes according to the indexes, and improves the data security in a power-off scene. Write amplification is reduced by introducing a lightweight index and adding a write strategy, and resource allocation and release are isolated through atomic operation. After the system crashes and is restarted, the consistent state of the file system is quickly rebuilt with high concurrency through a verification mechanism, snapshot replay and index recovery. The scheme has the advantages of low write amplification, high recovery efficiency, extensible architecture and the like.

The present invention includes apparatus and methods related to a data buffer in a non-volatile dual in-line memory module (NVDIMM). An example apparatus may include: a data buffer that can be coupled to a host; a first memory device (e.g., volatile memory), wherein the first memory device is coupled to the data buffer via a first bus; a second memory device (e.g., non-volatile memory); and a controller, wherein the controller is coupled to the data buffer via a second bus, and wherein the controller is configured to transfer data from the first memory device to the second memory device via the data buffer and the second bus.

A non-volatile dual in-line memory module (NVDIMM) supporting a DRAM cache mode and an operating method for the NVDIMM are provided. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory for the NVM chip. When the read latency (RL) of the DRAM chip and the write latency (WL) of the NVM chip are consistent with each other, the controller sends a read command to the DRAM chip with reference to the cache address of data requested to be written from the host to the NVM chip, and sends a write command to the NVM chip with reference to the address of the data requested to be written.