NVDIMM (Non-Volatile Dual In-line Memory Module) interface data read-write device for splitting CACHE

Abstract

The invention discloses an NVDIMM (Non-Volatile Dual In-line Memory Module) interface data read-write device for splitting a CACHE. In the method, a controller splits a DRAM (Dynamic Random Access Memory) into a DRAM_A and a DRAM_B; the controller enables any one of the split DRAM_A and DRAM_B to be under a data state and enables the other one to be under a command accepting state through a signalaccessory channel; when a host transmits data to a NVDIMM, the host has two states of connecting with the DRAM or the controller; when the host is connected with the controller, the host is under a command sending state; and when the host is connected with the DRAM, the host is under a data transmission state. The host of the invention is connected with any one of the following two states at anytime, wherein the first state is the DRAM_A and the DRAM_B of all capacity, and the second state is the DRAM_A (or the DRAM_B) of 1 / 2 capacity; after exchange is finished, switching is carried out forswitching time of the 100-nanosecond level, and the use ratio of the host for memory can be improved.

Description

technical field [0001] The invention relates to the technical field of computer storage, in particular to an NVDIMM interface data reading and writing device for splitting a CACHE cache. Background technique [0002] NVDIMMs can make general-purpose volatile memory modules (DIMMs) non-volatile. In the NVDIMM using the cache (CACHE) method, the capacity is much larger than that of the DIMM due to the use of non-volatile memory (such as NAND), while the speed characteristics retain the performance characteristics of the DIMM. From the perspective of the host, it is a large memory (the capacity of non-volatile memory), but the volume cost is much smaller than the DIMM of the same capacity. Big data applications such as databases are based on in-memory applications and require large-capacity memory. The DIMM memory capacity of the prior art is much smaller than that of non-volatile flash memory by more than an order of magnitude), and the price of the same capacity is much hig...

AI Technical Summary

Problems solved by technology

Since the access speed of NAND is slower than that of DRAM, and it does not have the definite access time of DRAM, when the data in NAND needs to be replaced to DRAM, the host must wait to access NVDIMM (the waiting time depends on the initial delay time (ten microseconds) and data exchange), which affects the efficiency of the host's use of memory

Images