Method for prefetching CPU cache data based on merged address difference value sequence

Abstract

The invention provides a CPU cache data prefetching method based on a merged address difference value sequence, which comprises the following steps of: collecting current memory access information of a to-be-prefetched data cache, and trying to obtain information from a historical information table to update and obtain a current difference value sequence section when the current memory access information is collected; according to the current difference value sequence segment, updating the historical information table, the difference value mapping array and the difference value sequence segment sub-table, and removing a first difference value to obtain a to-be-predicted difference value sequence; performing multiple matching on prefix subsequences of complete sequence segments stored in the dynamic mapping mode table by using the to-be-predicted difference value sequence to obtain an optimally matched complete sequence segment and a corresponding prediction target difference value; and adding the predicted target difference value to a memory access address in the current memory access information to obtain a predicted target address. The problem that in the prior art, multi-table cascading is needed to store the multi-length difference value sequence is solved, only one table is used for storage, and the storage and query logic of a memory access mode is simplified.

Description

technical field [0001] The invention belongs to the technical field of CPU chip hardware architecture, and in particular relates to a method for prefetching CPU cache data based on a combined address difference sequence. Background technique [0002] The high latency of CPU memory access is one of the main bottlenecks hindering its performance improvement. The cache data prefetcher predicts the data address required by the CPU for calculation, and loads the data from the memory into the cache in advance, thereby reducing the average memory access delay and improving the overall performance of the CPU. Among them, coverage, accuracy and timeliness are the three major elements to measure the performance of the prefetcher. [0003] Currently, mainstream prefetching method designs are mainly divided into two categories: Spatial prefetching and Temporal prefetching. Among them, Temporal prefetching has not been widely adopted in the industry because it requires too much hardwar...

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Problems solved by technology

[0004] The purpose of the present invention is to provide a CPU cache data prefetching method based on combined address difference sequences, to solve the problem in the prior art that multi-table cascading is required to store multi-length difference sequences, and only one table is used to save, simplifying The storage and query logic of the access mode

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