6 results about "Hit ratio" patented technology

This invention discloses a cache adjustment method, apparatus, device, and computer-readable storage medium, comprising: collecting access characteristic data from the client layer, object storage daemon layer, and device layer respectively; determining the object access mode of the system based on the access characteristic data; and adjusting the cache priority of each access task, the cache capacity ratio between the client layer and the object storage daemon layer, and the data residence time in the cache layer according to the object access mode; wherein the cache layer includes the client layer and the object storage daemon layer. This invention improves cache hit rate and overall read / write throughput performance, and reduces access latency.

A dynamic data loading method, a graphics processor, and a readable storage medium are disclosed. The dynamic data loading method includes: responding to a received data request, detecting the current operating mode of the caching module; the current operating mode is either a first mode or a second mode, where in the first mode the data request reads data in units of cache lines, and in the second mode the data request reads data in units of sub-blocks within a cache line; performing cache line miss detection based on the data request; in the current operating mode, determining whether to perform a cache line swapping operation based on the miss detection result; responding to the determination that a cache line swapping is triggered, performing the cache line swapping operation, and determining whether there is a need to switch operating modes; and determining whether to switch the current operating mode based on the number of times the cache line swapping operation is performed in the current operating mode and the number of times there is a need to switch operating modes. This solution can improve the performance and hit rate of the caching module.

This invention discloses a native parallel data packing method for 64-bit CPUs, belonging to the field of computer data representation and processing technology. This method packs eight 8-bit raw data columns into a standard 64-bit register, with each data column including 6 data bits and 2 carry bits. The raw data is expanded into a 64-bit data column through a bit extension step, and then packed into the 64-bit register using bit manipulation instructions to form 64-bit packed data. Inline functions are used to achieve zero function call overhead. The compiler automatically optimizes and generates efficient machine code, requiring no SIMD instruction set support. A lookup table method is used to achieve zero computational overhead packing; the lookup table contains 4096 entries. 64-byte cache row alignment is used to improve cache hit rate. Compared to traditional methods, packing and unpacking overhead is reduced by 6.6 times, from 11.3 ms to 1.7 ms. L1 cache hit rate is increased from 65% to 95%, memory access latency is reduced from 45 cycles to 12 cycles, and memory performance is improved by 3.75 times.

The application discloses a scheduling method and device of a virtual machine scheduling domain, equipment and a storage medium. First, the number of VCPU required by a to-be-scheduled virtual machine in a target processor is obtained to obtain core requirement number, and a scheduling domain binding strategy is determined based on the core requirement number. A plurality of PCPU corresponding to each L3 Cache in the target processor is obtained, and a topology information table is constructed based on the corresponding relationship between them. Then, the actual available states of each PCPU included in the topology information table are determined, and the PCPU with an idle state as the actual available state is determined as a target core. Then, all target cores are grouped based on the corresponding L3 Cache of each target core in the topology information table to obtain a plurality of candidate core groups, so that the above strategy and the plurality of candidate core groups are used for scheduling domain binding of all VCPU. The application can improve the processor cache hit rate, reduce the data access delay, and further improve the overall running performance of the virtual machine.

The application discloses a kind of based on layered learning index's multi-ndp equipment read-write acceleration method and system, method includes: in host end to key-value heat identification, in NDP equipment end executes key-value separation, respectively write hot value log area or cold value log area;Layered learning index is constructed and maintained, the value address of target key is positioned, and in multi-level cache collaborative management system is inquired;When the invalid data proportion of value log file reaches threshold, trigger garbage collection task.The application introduces learning index, accurately locates key-value address, converts multiple random reading of point query into small range sequential reading, significantly reduces read delay.Key-value separation and write heat identification are used to realize cold and hot data shunting writing, reduce write amplification.Multi-level collaborative cache mechanism based on migration benefit score is designed, dynamically optimizes the distribution of hot data between host and device, improves cache hit rate.Inefficient data is tracked and parallel recovery is triggered, improving storage space recovery efficiency, thereby systematically optimizing read-write performance.