4 results about "Miss rate" patented technology

This invention provides a streaming data management method and apparatus for a reconfigurable processor multi-port cache, relating to the field of large-scale integrated circuit technology. The method includes: when processing a cell array accessing the cache, if a cache miss occurs, evicting a cache line with a target bit set to a first preset value using a polling arbitration method, and setting the target bit of subsequent cache lines entering the cache to the first preset value; when processing a cell array accessing the cache, if a cache hit occurs, setting the target bit of the currently hit cache line to a second preset value based on the interval between the previously hit cache line and the currently hit cache line. This invention can effectively reduce the probability of cache thrashing under the flushing of streaming data, thereby reducing the frequency of accessing off-chip memory, increasing the memory access bandwidth of the PEA, mitigating potential conflicts and misses caused by set-associations, and reducing the miss rate for streaming data.

Methods, systems, and devices for a partitioned cache for random read operations are described. Implementations may determine a target compression factor that is used during read operations. Larger compression factors may be associated with more frequent penalties, but may allow for a larger high-performance benchmark on a large address range. As described herein, a compression factor may indicate certain mappings that are stored to a volatile memory. The compression factor may be chosen at product design time or may be chosen dynamically at run time based on statistics such as extended cache hit or miss rate. If a read command associated with a logical block address not stored by the volatile memory is received, the memory system may “guess” the physical address by assuming that data was written to the memory system sequentially. If the data is correct, the data may be read out to the host system.

The present application relates to the field of computer technology, and relates to an adaptive method, device, and medium based on Warp scheduling and cache replacement. The method includes: dynamically monitoring the access behavior of Warp in the L1 data cache through a locality perception unit to identify the locality preference of the workload; adaptively selecting a Warp scheduling algorithm based on the locality preference; periodically collecting cache access counts and cache miss counts through a cache status monitor, calculating the memory access miss rate of the current sampling period, and comparing it with the miss rate of the previous sampling period; if the memory access miss rate of the current sampling period is higher than that of the previous sampling period, switching the cache replacement strategy; if it is lower than or equal to, maintaining the current strategy. The present invention adaptively adjusts the Warp scheduling algorithm and cache replacement strategy to optimize the cache utilization and performance of the GPGPU.

For a given application, increasing the size of a cache is beneficial up to a certain point and the number of hits does not increase significantly with a greater cache size. This disclosure provides a method to determine a miss ratio curve, for a cache having data blocks with a time-to-live. A hashed value of a data block's key address can be used to generate a 2D HLL counter for storing expiry times of the data blocks. The 2D HLL counter can be converted to a 1D array, from which a stack distance can be calculated. A frequency distribution of stack distances can then be converted into a miss ratio curve, from which an appropriate cache size can be selected.