Method for dynamically partitioning shared cache in multi-core environment

Abstract

The invention discloses a method for dynamically partitioning a shared cache in a multi-core environment. The method comprises the following steps of: initializing a hardware counter, starting a plurality of applications, sampling running information of the applications by using the hardware counter, obtaining basic block information of the applications by using the hardware counter, analyzing phase behaviors of the applications, judging whether phases of the applications are changed or not through extracting the IPC (Instruction Per Cycle) coefficient of variation of the applications, obtaining cache miss pitches of the applications by using the hardware counter if the phases of the applications are changed so as to obtain miss rate curves, establishing cache partitioning strategies for the applications according to the miss rate curves, and reallocating caches of the applications by using a dynamic page coloring method according to the established cache partitioning strategies. According to the method, the cache demand changes of the applications can be perceived, so that the caches of the applications are subjected to adjustment at the best time; and furthermore, compared with the existing phase behavior analysis method, the method has the advantages that the performance of the applications is hardly affected, and the overall performance of a system can be effectively improved.

Description

technical field [0001] The invention belongs to the field of multi-core system structure and program behavior analysis, and more specifically relates to a dynamic division method of a shared cache in a multi-core environment. Background technique [0002] On-chip multi-core processors (Chip Multi Processors, CMP) have become the mainstream of microprocessors due to their advantages of high performance and low power consumption. As the core part of the processor, the cache plays a vital role in the performance of the processor system. Under the multi-core architecture, the processor adopts a multi-level cache design method, and all processor cores share the last-level cache or each processor core has its own private last-level cache. The structure of the private last-level cache has good chip scalability and relatively simple control logic, but it cannot make efficient use of system resources. In comparison, the structure of the shared last-level cache has the advantages of...

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Problems solved by technology

[0007] (1) It is not possible to adjust the program cache at the most appropriate time, because the program's cache requirements are related to the program's stage behavior, and the program's stage behavior is not uniform and regular. Making adjustments does not make adjustments to a program's cache at the optimal time when its cache requirements change;

[0008] (2) Dynamically adjusting the cache requires dividing the program into a cache of an appropriate size. To determine whether the cache size is appropriate, the existing mechanism needs to add additional hardware to monitor the memory access behavior of the program. This method cannot be applied to real on the machine

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