137 results about "Error reporting" patented technology

The invention discloses an intelligent news content error correction system based on a large model, particularly relates to the technical field of big data, and aims to extract key entity information of figures, positions and institutions in news texts and identify time sequence feature words in position description so as to identify association relationships among entities; historical job change records and latest information are obtained from multiple data sources, reliability scoring is performed through a large model, a multi-modal evidence chain with time sequence attributes is constructed, a prediction model is trained based on historical job data, the change probability of a specific job in a future time period is calculated, and space-time consistency of job information is analyzed. And in combination with the output change probability, identifying errors by comparing a multi-source evidence chain, implementing priority verification on a high-probability change event, generating a hierarchical error report, outputting a correction suggestion, updating an error correction result in real time, implementing two-factor authentication on the correction suggestion, and storing a typical job change mode and a correction scheme by creating a historical case library.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

The invention discloses a large model query generation system and method combining graph structure analysis and execution, and the system comprises a graph mode standardization module which converts a description file into a unified structured representation; the large language model module is used for screening out nodes, edges and sub-graph modes required by query statements according to the natural language problem and the structured representation of the user; the graph mode detection module is used for detecting and modifying the screened nodes, edges and sub-graph modes through scripts; the large language model module generates an initial query statement according to a natural language problem of a user and detected and modified nodes, edges and subgraph modes; the query statement detection module is used for detecting the initial query statement through a script and generating an error report; and the large language model module generates a modified query statement. According to the large model query generation system and method combining graph structure analysis and execution, the accuracy of graph mode selection is remarkably improved through the thinking ability of the large language model and the script error detection ability, and therefore the quality of graph database query statement generation is improved.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

An example operation may include one or more of receiving a report of an error from an installation process of a software program as the installation process is being performed by a computer, executing an artificial intelligence (AI) model to predict at least one instruction to fix the error based on the report of the error, and presenting the at least one instruction via a graphical user interface of the computer associated with the installation process.

The invention discloses an automatic testing system and method for a modular interface, and relates to the technical field of interface testing, and the system comprises an interface analysis module which is used for loading a to-be-analyzed interface document and extracting interface basic information from the to-be-analyzed interface document; the test case generation module is used for generating test cases of normal and abnormal scenes based on the interface basic information and a preset case template; the interface information comparison module is used for automatically detecting updating of an interface document, positioning changed content and synchronously updating a test case before the test is executed; the test execution module is used for executing an interface test by calling a test tool or a built-in Selenium interface automation framework; the test data analysis module is used for collecting test data generated in a test process in real time, and calling AI model analysis to quickly position an interface error reason; and the test document output module is used for summarizing the test data and the AI analysis result and generating a test report in multiple dimensions. According to the invention, the test and maintenance work of various interfaces can be rapidly and accurately completed.

The invention relates to a multi-node memory synchronization method and device, equipment, a storage medium and a program product. The method comprises the following steps: establishing connection among nodes in a distributed system, configuring local / far-end queues for recording the busy degree of a thread for each node, creating a queue pair associated with a unique doorbell address for each node in combination, and optimizing a retention rule and an error reporting mechanism of a working queue element (WQE) in the queue pair, so that the busy degree of the thread is recorded; batch synchronization of multi-node memory data is achieved by adding an RDMA write operation WQE recording the busy state of a thread before a far-end mapping memory area is newly added and triggering hardware to execute RDMA write operations corresponding to all WQEs in a queue pair in sequence when the busy state of a local thread is updated. By the adoption of the method, the switching frequency of a CPU core between the synchronization task and the calculation task can be reduced, efficient, low-overhead and high-reliability multi-node memory synchronization is achieved, and the method meets the performance requirement of a large-scale distributed system.

The invention discloses an information processing method, a chip system and electronic equipment, the chip system comprises a plurality of core particles, in each processing period, one core particle in the chip system is configured as a main core particle, the other core particles are configured as slave core particles, and the information processing method comprises the following steps: when the slave core particles obtain error information, the error information is sent to the chip system; determining, by the slave core particle, an information level of the error information; and under the condition that the information level meets the error reporting condition, the error information is sent to the main core particle by the slave core particle, so that the error information is processed by the main core particle.

In various examples, static single assignment-based control flow graph traversal analysis for uninitialized variable detection system and methods are disclosed. A pre-compiler stage of a compiler system, may reconstruct source code into an SSA form IR and detect and identify uninitialized variables based on applying a variable analysis pass that traverses a CFG corresponding to the SSA form IR. A variable analysis pass may traverse through the CFG to build a defined variable map and a Phi variable map. The maps may be used to map undefined variables to basic blocks of the CFG where the undefined variables occur. The variable analysis pass may pass uninitialized variable data to a compiler error handling process. The compiler error handling process may produce an error report that traces the basic block with undefined variables to lines of the source code to assist in efficiently debugging the source code.

The invention discloses a processing method for correctable errors of a graphics processor and electronic equipment, relates to the technical field of servers, and aims at the graphics processor to determine a flexible processing strategy for correctable errors from double angles of error reporting time and error reporting times, so that the occupation of correctable error processing on the processor and bus resources is greatly reduced. Based on an intelligent time window and time threshold mechanism, the method can distinguish instantaneous interference from hardware faults, so that excessive interference of accidental errors on the system is avoided, the problem of hardware degradation can be warned in advance, and sufficient time is won for system maintenance.

In a wireless communication system, at least one UE detects GNSS signal spoofing / jamming and reports a detected spoofing / jamming attack to a server in the network apparatuses using an extended LPP GNSS error reporting format with an additional error cause and an attack probability metric. Further, the network apparatuses may take an implementation-dependent decision depending on crowd-sourced information of one or more spoofing / jamming attack reports received from one or more UEs.

Implementations for chiplet fault management through hierarchical error reporting and coordinated recovery in an accelerator interconnect. In some implementations, a system for a UALink-based network comprises a chiplet die coupled to an accelerator die, a management agent on the accelerator die, and a centralized controller. Upon fault detection, the chiplet die transmits a fault notification to the accelerator die, the management agent reports the fault to the centralized controller, and the centralized controller determines a recovery action based on the fault identifier and severity. In some implementations, the accelerator die reports the fault through dual paths, to a host processor via CXL or PCIe error reporting and to the centralized controller via the management agent, and the host processor and the centralized controller coordinate recovery, with the host managing workload-level recovery and the centralized controller managing network-level recovery.

The invention discloses an Excel data verification processing method and system based on dynamic annotation configuration, and relates to the technical field of data verification. The method comprises the following steps: after receiving an Excel file uploaded by a user, dynamically analyzing entity class annotation configuration data through a reflection mechanism to obtain a (at) Excel CheckProperty annotation labeled for an Excel column field, initializing a verification rule based on an analysis result, then performing batch data analysis processing on the Excel file to obtain current batch data to be verified and containing multi-row information, and performing data verification on the current batch data to be verified. The method comprises the following steps: initializing a verification rule, sequentially traversing and verifying each row of information in the current batch of data by applying the initialized verification rule to collect abnormal information, and finally, after all batches of data are verified, generating and outputting a data verification error report based on all the collected abnormal information. Therefore, the method has the advantages of configurable verification rule, high processing efficiency, high error positioning precision and / or low memory consumption and the like, and is convenient for practical application and popularization.

Embodiments of the present application provide a register state monitoring system, method and product. The system comprises: a static monitoring module configured to, according to register information of any first register in a static monitoring linked list, send an error reporting message corresponding to the first register to an error recovery module when a state error of the first register is monitored; a dynamic monitoring module configured to, according to register information of any second register in a dynamic monitoring linked list, send an error reporting message corresponding to the second register to the error recovery module when a state error of the second register is monitored; and the error recovery module configured to, in response to the error reporting message corresponding to the first register, recover a state value of the first register, or in response to the error reporting message corresponding to the second register, recover a state value of the second register. Embodiments of the present application aim to improve the efficiency of the error recovery process.

The invention provides a cross-application Excel data import processing method and system based on cloud storage, and relates to the technical field of data processing.The method comprises the steps that a processing request of an Excel file from a front-end service application is received through a unified service center; generating a pre-signature URL of the Alicloud OSS, and returning the pre-signature URL to the front end; the front end directly uploads the Excel file to the Alicloud OSS; based on the system configuration record, performing Excel file configuration matching to obtain complete configuration information; based on a Rocket MQ Tag mechanism, delivering the message meeting the condition to a corresponding target business application; the target business application automatically analyzes the Excel file; performing data verification and business logic processing on the analyzed Excel file; counting service logic processing results and generating an error report; and notifying the unified service center to update the processing state according to the business logic processing result.

This application discloses a method and electronic device for error reporting on a processor platform, relating to the field of computer hardware technology. The method includes acquiring multiple error identifiers of the processor platform, which characterize the types of faults encountered by the platform. Based on historical data and real-time operating parameters, a predictive model is constructed. This model improves the predictive maintenance capabilities of the processor platform. Then, based on the error identifiers and the predictive model, the types of faults that the processor platform may experience in the future are determined. Therefore, this method solves the technical problem in related technologies where it is difficult to provide early warnings of potential faults in processor platforms. It achieves the technical effect of timely detection of impending faults in the processor platform, allowing for timely handling based on the prediction results, and avoiding the loss of opportunities to take preventative measures before faults occur.

The invention discloses a Cadence Skill-based automatic creation method and system for a depth-controlled milling groove distribution forbidding area of a PCB connector, and a medium, and belongs to the technical field of electronic printed circuit board design, and the method comprises the steps: generating the lamination number and depth of the milling distribution forbidding area corresponding to a hollow area according to the creation data, processing parameters, geometric shape and installation hierarchy of a target PCB connector; carrying out groove milling processing on the target PCB connector according to the lamination number and depth of the milling distribution forbidding area, and simultaneously carrying out error reporting prompt on wiring, via holes and copper sheets in the hollowed area; the overhanging amount of the pins of the processed target PCB connector is greater than or equal to a preset welding pin safety distance, and the residual board thickness of the non-milling area is smaller than the effective embedding length of the pins. According to the invention, the problems of low efficiency, high miscalculation risk, poor groove milling consistency and signal failure caused by the fact that the establishment of the existing PCB connector pin distribution forbidding area depends on manual operation are solved.

The invention discloses a system for judging the over-slaughtering degree. The system comprises a wafer yield tester, a server and an employee device, the server is electrically connected with the wafer yield tester and comprises a test database, a training database, an over-slaughtering judgment processor and an error notification processor. The over-slaughtering judgment processor is electrically connected with the training database and the test database and is configured to execute over-slaughtering check on the test initial coding data according to the historical over-slaughtering data so as to judge whether the over-slaughtering degree in the wafer probe test exceeds an allowable range or not. The error notification processor is configured to transmit an error report. The employee device is electrically connected with the server and is configured to receive the error report. Some embodiments of the invention also provide a method for judging the over-slaughtering degree. By means of the over-slaughtering judgment processor and the error notification processor, the crystal grains can be prevented from being mistakenly slaughtered, and the time required for over-slaughtering inspection is shortened by scanning and testing the initial coded data.

The invention relates to the technical field of combination of bridge building finite element modeling and an artificial intelligence large model, in particular to a finite element modeling error diagnosis and automatic correction method and system. The method comprises the following steps: constructing a pre-training finite element large model and a structured finite element error corpus; receiving finite element modeling error reporting information input by a user, and judging an error type corresponding to the error reporting information based on the pre-trained finite element large model and the structured finite element error corpus; searching a matched candidate repair scheme in a structured finite element error corpus according to the error type; integrating and optimizing the candidate repair schemes through a pre-trained finite element large model to generate a target correction scheme; and outputting the target correction scheme to a user side to complete diagnosis and automatic correction of finite element modeling errors. The problems that finite element error reporting information is obscure and difficult to understand, and engineers are difficult to position quickly are solved.

Systems and methods are described that allow for updating of software applications during testing of the application to detect errors as a result of execution of portions of the software application that prevent downstream portions of the software application from being evaluated. In an example, systems are described that are configured to detect errors during application execution. When an error is detected, the system obtains and executes specific script sets to debug the application. Based on the results of these debug operations, the system generates error reports that indicate issues within the software workflow. This ensures that errors in one part of the software do not hinder the evaluation of subsequent parts, allowing for a more efficient and thorough testing process.

The invention discloses a software testing method for software and hardware interaction, which belongs to the field of software testing and comprises the following steps of: acquiring an interaction signal data string sent to a software module through a data interface when a hardware module executes different functions from the data interface; the error tag probability of the hardware module when different historical interaction signals are represented is calculated, and the mapping relation between the historical interaction signals and the error tag probability is obtained; screening a historical interaction signal data string most similar to the collected interaction signal data string, and obtaining a contrast probability for evaluating the repair capability; generating a test case set; and according to the error reporting probability of the hardware module, evaluating the repairing capability of the software. According to the method, the generated test case not only keeps the real-time interaction signal characteristics, but also has the characteristics of historical interaction signals, so that the comprehensive test and evaluation of the software repair performance are realized; and the comprehensive and accurate repairing capability after the new software is applied to the hardware module is ensured.

A system includes a memory component for writing flag bits into a set of memory cells programmed by a multi-pass programming command after a second programming pass has been completed in response to such a command. A processing means operatively coupled to the memory component is used to perform the multi-pass programming of the set of memory cells in association with logical addresses. Upon receiving a read request, the processing means determines that a second logical address within the read request does not match the logical address associated with data stored at a physical address in the set of memory cells. The processing means further determines the number of first values ​​within the plurality of flag bits, and reports an uncorrectable data error to a host computing device in response to the number of first values ​​not meeting a threshold criterion.

Accuracy, efficiency, and speed improvements for error alerting are provided herein, particularly in the context of error detection and alerting. There are provided systems and methods for scalable error alerts threshold based on conversion metrics for data processing flows. A service provider may utilize different computing services for data processing to provide different computing services to users, such as via websites and / or applications of the service provider. Due to timeouts, failures, and other errors, users may be unable to complete a data processing flow. To provide dynamic error alerting, thresholds for reporting of the errors may be adjusted based on conversion metrics for users abandoning the processing flow at different steps. A threshold for a number of users that fail to complete the flow at certain steps may be adjusted to account for users that may abandon due to errors or other reasons.

The application discloses a radar voice interaction control method and system based on natural language processing, relates to the technical field of voice recognition, and solves the technical problems that it is difficult to combine radar echo signals with hyperspectral image data to detect target states, it is difficult to realize voice interaction control by using natural language processing, it is difficult to reasonably determine the priority of control instructions based on an environment comprehensive coefficient and an emergency degree value, it is difficult to establish a conflict detection mechanism to ensure the feasibility of instructions, and it is difficult to execute instructions under the conditions of multi-target game and dynamic priority change and monitor and evaluate deviation values to establish an error reporting mechanism. The application realizes target state detection by fusing radar echo signals and hyperspectral image data, realizes voice interaction control by using natural language processing, and dynamically generates hierarchical control signals in combination with an environment comprehensive coefficient and an emergency degree value.

The invention discloses a layout test rule checking method and device, and the method is carried out in a layout design process, and comprises the steps: S1, carrying out the type recognition and port position searching of a device of a layout in a code form; and S2, verifying the position of the port of the device according to the test rule, and reporting an error for the device which does not accord with the test rule. According to the invention, timely error reporting in the layout design process is realized, and timely error correction of a designer is facilitated, so that the layout design and test efficiency is improved.

The invention provides an automatic identification processing method and system for errors of a photoetching machine. The method comprises the following steps: sequentially performing position coarse alignment, inclination amount detection, position fine alignment and exposure on a wafer of the photoetching machine; replacing an alignment image acquisition area, an alignment mode and an alignment mark if position coarse alignment or fine alignment is unsuccessful, and replacing an exposure focal plane position, a focusing mode and a focusing position if inclination amount detection reports errors; if exposure is abnormal and fine alignment is performed on the complete acquisition area, the focusing mode and the focusing position are replaced, and if fine alignment is performed on the incomplete acquisition area, the previous exposure value is used; and if the action of the photoetching machine is abnormal, stopping the action and giving an alarm. According to the invention, detection parameters of coarse alignment, inclination amount detection, fine alignment and exposure abnormity of the wafer of the photoetching machine are automatically adjusted, the unnecessary error reporting downtime frequency of the machine is reduced, and the influence of shutdown of the machine on the running amount and the wafer quality is avoided; and meanwhile, the standing time, batch number and error signals of the wafer are monitored to find machine abnormity in time, so that the loss caused by abnormity of a certain module of the machine is reduced.

Apparatuses and techniques for controlling error reporting for usage-based-disturbance mitigation are described. In an example aspect, an adaptable method of controlling error reporting is provided so as to account for an uncertainty regarding a level of intermittent faults associated with a memory device. An error-reporting control circuit provides a mechanism to control how often errors are reported to a host device. In particular, the error-reporting control circuit can filter unnecessary noise associated with intermittent faults based on a parameter that is settable (e.g., programmable or changeable). In this manner, the error-reporting control circuit can provide further confidence at the host device that reported errors are associated with permanent defects. Furthermore, the parameter can be appropriately set for the given memory device based on its design and / or architecture once silicon data is available.

The embodiment of the invention provides an equipment fault processing method, a host, a computer program product and a storage medium. The operating system of the target host can run an error report driving program after receiving an interrupt signal sent by any root interface and used for triggering an error report mechanism; based on an error report driving program, obtaining an address translation exception record from an event queue maintained by a memory management unit; if the address translation exception record points to any virtual device connected to the root interface, calling a kernel mode drive program corresponding to the virtual device through an error report drive program; and controlling the target virtual machine served by the virtual equipment to be paused based on the kernel mode driving program. Therefore, when a single virtual device has a fault, the fault domain can be accurately controlled on the virtual machine served by the faulted virtual device, so that only the virtual machine served by the faulted virtual device is suspended, and the influence on other virtual machines running on the target host can be effectively avoided.

The present disclosure provides an automatic error-reporting tracing method and apparatus, a storage medium and an electronic device. The automatic error-reporting tracing method comprises: determining whether a running test case has triggered error reporting; when the test case has triggered error reporting, performing tracing to acquire execution information corresponding to the error reporting; and on the basis of the execution information, performing matching in an error reporting-regression test suggestion database so as to obtain a regression test suggestion. The embodiments of the present disclosure can trace error reporting in vehicle-mounted operating systems, so as to determine the positions of modules where errors have occurred and analyze the errors, and can provide corresponding regression test suggestions for the causes of error reporting. For common errors, automatic regression test scripts are given such that regression tests can be performed automatically.

This invention provides a database testing method, apparatus, electronic device, and storage medium based on protocol layer interaction. It generates test SQL statements, performs parameterization to form parameter placeholder structures, and extracts parameter constraint information. Based on the parameter placeholder structures, parameter constraint information, and the current session state, it generates protocol test cases, sequentially sends multiple protocol data packets, receives and parses response data packets returned by the database system, records communication error information during response reading, and updates the current session state based on the parsing results of the response data packets. When the communication error information is detected during response reading, if a crash occurs or the verification results are inconsistent, an error report is generated. This invention can cover protocol processing paths under different execution stages and interaction sequences, reduce invalid requests with semantically invalid or easily rejected requests, improve the validity of test input, and enhance the coverage depth and defect detection capability of database protocol testing.