30 results about "System Management Mode" patented technology

A host server computer with an uncorrectable memory error can be repaired without a reboot operation. While initially booting a hypervisor, a special software Application Programming Interface (API) can be loaded between a BIOS System Management Mode (SMM) code and the hypervisor. Once the host server computer is booted and a number of virtual machines are executing, a memory error (e.g., uncorrectable error correction code (UECC)) can occur. In response, the hypervisor calls into the special software API identifying the defective memory rows that the BIOS needs to repair. The BIOS starts a soft Post Package Repair (PPR) process on those rows and gives back control to the hypervisor. When the repair is completed, the hypervisor loads a scrubbing virtual machine and validates that the memory is corrected. After the repair is validated, the hypervisor allows the available partition to take a new customer instance.

The invention discloses a system manager, an error data processing method, error data processing equipment and a program product, and relates to the technical field of data process.A processor is used for writing error data corresponding to a system error into an error information storage area when the system error is detected, and a controller is used for writing the error data corresponding to the system error into the error information storage area when the system error is detected. And the alarm module is used for reading the error data stored in the error information storage area and generating alarm information when the error data meets a preset condition, so that transmission and efficient asynchronous communication of the error data are realized through the error information storage area and the interrupt register, the preset condition is added, and the alarm information is triggered when the preset condition is met. The processor is prevented from entering a system management mode, meanwhile, performance jitter of an operating system caused by frequent system management interruption is reduced, and the efficiency of processing error data by the system is improved.

An apparatus is disclosed. The apparatus comprises one or more processors to receive a request to trigger a system management interrupt (SMI), execute policy shim code to enforce access control policy in a first privilege level and dispatch the SMI to shield code to enforce the access security policy to perform a system management mode (SMM) and execute the shield code to perform the SMM, including retrieving an operating system (OS) memory preserved warm reset (MPWR) context, saving the context and issuing a warm reset.

The application provides an IPMI command processing method, device, system and electronic equipment. The method comprises the following steps: obtaining state information of a BMC; determining whether the BMC is currently in a fault state according to the state information of the BMC; triggering an interrupt signal and transmitting the interrupt signal to a BIOS to modify the IPMI retry count of the BMC to a preset minimum IPMI retry count based on the BIOS in the case that it is determined that the BMC is currently in the fault state; and exiting a system management mode when the IPMI command retry count reaches the preset minimum IPMI retry count. The BMC is detected in the fault state, and the IPMI retry count is modified to the preset minimum IPMI retry count in the case that it is determined that the BMC is faulty, so as to reduce the number of repeated IPMI command transmissions and shorten the running time of the server in the system management mode, thereby improving the server system performance.

The disclosed technology is directed to a computing device for handling system management interruptions if an emergency response is desired. In some examples, a computing device includes a memory controller and a processor. The memory controller, in response to determining that the memory access matches the attack pattern, sets the register to a value and triggers a system management interrupt. When a system management interrupt is detected, the processor causes the first thread to enter a system management mode. The first thread then accesses the register. A power reset on the computing device is triggered in response to determining that the register is set to the value without waiting for remaining threads to enter a system management mode.

Systems and methods are provided for implementing improved root cause analysis (“RCA”)-based node recovery. After instructing a node to enter a debug mode and based on a determination that an expected response timeout duration has elapsed, a controller instructs the node to enter a system management mode (“SMM”), and exposes a shared buffer to an SMM handler of the node. The shared buffer includes instructions for the SMM handler to set a trap flag in a saved state area of an operating system (“OS”) of the node and to use a resume execution instruction after setting the trap flag. The trap flag causes the OS to transfer control of problematic code to a trap handler, which performs operations or calls a hypervisor for a virtual machine extension (“VMX”) root mode depending on whether the problematic code execution occurs in a non-maskable interrupt (“NMI”) handler.

The invention discloses a BIOS firmware security verification method and system based on a trusted execution environment, and belongs to the technical field of computer security, the BIOS firmware security verification method comprises the following steps: obtaining a complete mirror image, a key configuration variable and a system management mode code snippet of BIOS firmware, and processing data in the trusted execution environment to generate a trusted baseline snapshot; monitoring a high-risk system event, and triggering the verification of the running state of the BIOS according to the high-risk system event; reading data in the current memory and comparing the data with the trusted baseline snapshot to generate a tampering detection result and abnormal behavior judgment; and executing hierarchical response according to the threat level, and executing a hot repair operation for a high threat event. According to the method, the trusted execution environment is adopted to realize monitoring and active repair during operation, malicious tampering in the memory can be found and repaired immediately, and the safety and reliability of BIOS firmware during operation of an operating system are improved.

The specification provides a memory power consumption configuration method, device and equipment and readable storage medium, the method comprises: in response to SMI interrupt, enter system management mode SMM, write function field for configuring memory power to memory power register;According to the target power parameter in the function field, configure the memory power consumption limit;If CPU usage is equal to or higher than the idle threshold, write the first power parameter as the target power parameter, and the memory runs at the first rated working frequency corresponding to the first power parameter;The idle threshold is pre-set;If the CPU usage is lower than the idle threshold, write the second power parameter as the target power parameter, and configure the memory working frequency to make the memory run at the second rated working frequency corresponding to the second power parameter;The second power is lower than the first power. Through the technical scheme of the specification, the power waste when the CPU usage is low can be effectively avoided.

Systems and methods to support system management mode (SMM) update and telemetry in runtime for bare metal deployments. During runtime operation of a host operating system on a bare metal platform having a management controller and including a processing unit on which the host operating system (OS) and host BIOS are executed, an out-of-band runtime update is performed to update secure execution mode (e.g., SMM) runtime firmware for the bare metal platform using an out-of-band channel comprising an interrupt driven, shared memory-based data exchange channel between the management controller and the host BIOS. This enables secure execution mode runtime firmware to be updated without during runtime without having to reboot the platform or restart the OS kernel. The out-of-band channel also supports exchange of telemetry data logged by the host BIOS during the runtime update with the management controller.

An electronic device and a method for managing micro-operations are provided. In an embodiment, the method includes determining, by a processing unit, whether a micro-operation corresponding to a translation instruction is stored in a translation buffer and a micro-operation cache when the processing unit executes the translation instruction; outputting, by the processing unit, a specific micro-operation to enter a system management mode when the micro-operation corresponding to the translation instruction is not stored in the translation buffer and the micro-operation cache; translating, by the processing unit, the translation instruction into the micro-operation corresponding to the translation instruction in the management mode; and storing, by the processing unit, the micro-operation corresponding to the translation instruction into the micro-operation cache.

Disclosed herein is a system for limiting the rate at which a system management interrupt can suspend normal execution of a central processing unit (CPU) by switching the operating mode of the CPU from one of a real mode or a protected mode to a system management mode. The rate limit imposed by the system provides a protection against network attacks (e.g., distributed denial of service (DDoS) attacks) from malicious behaviorists, and ensures that the CPU may be more efficient in executing workloads (e.g., processing threads).

Provided in the present application are code sharing methods and apparatus, a switch, a multi-host system, a device and a medium. A method comprises: determining to enable a system management mode of the current host; sending a system management mode initialization request to a switch in a multi-host system, the switch being used for determining, on the basis of the system management mode initialization request, a target shared memory module for storing system management mode code from among a plurality of shared memory modules in the multi-host system and a system management random access area in the target shared memory module corresponding to the system management mode code, and establishing a data connection between the current host and the target shared memory module; and, on the basis of the system management mode code, initializing the system management mode of the current host.

A system is disclosed for Input / Output (I / O) device emulation that allows a service provider to configure and enforce a policy for software access to some or all I / O resources in a platform. I / O device emulation enables service providers to protect their platforms from malicious guest software that may be executed on associated platforms that has direct access to I / O resources in case of bare-metal servers, escalates the privilege level from guest to host in case of hosted-Virtual Machine servers, or escalates the privilege level from guest to System Management Mode in case of either bare-metal servers or hosted-Virtual Machine servers. The technology enables service providers to protect their platforms from malicious guest software running on their platforms that either has direct access to legacy I / O and memory mapped I / O resources. In one illustrative example, the platform may include a microprocessor.

The present invention relates to a method for a processor and a computer system to enter system management mode (SMM). The method is applied to the processor, which includes at least one logical core. The method includes entering the SMM in response to a system management interrupt (SMI), storing current state information to a corresponding state save area; setting operation mode to target operating mode, and executing the SMI handler under the target operating mode. The address of the state save area, the address of the core configuration information memory space, and the address of the SMI handler can be determined directly. Each logical core may enter the target operating mode directly through hardware setting every time after entering the SMM, and thus does not need to perform a fixed operation of mode switching when executing the SMI handler, which may improve the execution efficiency of the SMI handler.

Examples described herein relate to an interface and a core coupled to the interface, wherein based on a configuration, the core is to respond to an interrupt indicating an error by outputting error data to a management controller while permitting thread execution on the core. In some examples, based on the configuration, the core is to invoke the management controller to handle errors and not enter System Management Mode (SMM).

The present application relates to the technical field of servers, and discloses a system management memory allocation method, a program running method, a system, and a product. The system management memory allocation method comprises: starting a basic input / output system, initializing a system management mode environment, and configuring a system management mode service; acquiring a number of physical processors of a server on which the method located, and a number of cores carried by each physical processor, and calculating a total number of cores; on the basis of the total number of cores, determining a corresponding core interval, and on the basis of the core interval, determining a first target capacity of a system management memory to be configured; on the basis of the first target capacity, allocating system management memory for driving updates in a system management mode. Using the present method, flexible and automatic SMRAM memory allocation for servers having different hardware configurations can be implemented, so as to satisfy normal operation of an SDU.

A system is disclosed for Input / Output (I / O) device emulation that allows a service provider to configure and enforce a policy for software access to some or all I / O resources in a platform. I / O device emulation enables service providers to protect their platforms from malicious guest software that may be executed on associated platforms that has direct access to I / O resources in case of bare-metal servers, escalates the privilege level from guest to host in case of hosted-Virtual Machine servers, or escalates the privilege level from guest to System Management Mode in case of either bare-metal servers or hosted-Virtual Machine servers. The technology enables service providers to protect their platforms from malicious guest software running on their platforms that either has direct access to legacy I / O and memory mapped I / O resources. In one illustrative example, the platform may include a microprocessor.

The present application provides a code sharing method and apparatus, a switch, a multi-host system, a device, and a medium. The method includes: determining to enable a system management mode of a current host; sending a system management mode initialization request to a switch in a multi-host system, where the switch is configured to determine, based on the system management mode initialization request, a target shared memory module for storing system management mode code among a plurality of shared memory modules in the multi-host system, and a system management random access memory area corresponding to the system management mode code in the target shared memory module, and establish a data connection between the current host and the target shared memory module; and initializing the system management mode of the current host based on the system management mode code.

The present application discloses a system manager, an error data processing method, a device and a program product, and relates to the technical field of data processing. Since the processor is used to write the error data corresponding to the system error into an error information storage area when a system error is detected, the controller is used to read the error data stored in the error information storage area and generate an alarm message when the error data meets a preset condition. Therefore, the transmission of error data and efficient asynchronous communication are achieved through the error information storage area and the interrupt register, and a preset condition is added. When the preset condition is met, the alarm message is triggered, thereby avoiding the processor from entering the system management mode, and at the same time reducing the performance jitter of the operating system caused by frequent system management interrupts, thereby improving the efficiency of the system in processing error data.

An information handling system receives a system management interrupt (SMI), and if an SMI telemetry is enabled, then the system reads a first timestamp at an entry point of the SMI. Subsequent to handling the SMI, the system reads a second timestamp at an exit point of the SMI, and calculates a system management mode latency based on a difference between the second timestamp at the exit point and the first timestamp at the entry point.

The present invention discloses a server and a method, device, medium and program product for processor error handling, relating to the technical field of servers. The method includes: when a correctable error occurs in the processor, displaying a setting interface including error parameter configuration options, and setting a target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options; in an execution environment corresponding to the system management mode, selecting error severity data corresponding to the processor from multi-device error collection information according to error type identifiers assigned to different errors by an error register; determining whether to generate an error reporting and clearing instruction according to the processor error severity data and the target fault tolerance allowable value. The present invention can solve the problem in the related art that error reporting cannot be decoupled, resulting in untimely discovery of CPU CE faults. Users can perceive the CE error type, which is beneficial to improving the accuracy and efficiency of fault identification, reducing the probability of CE storms, and enhancing the reliability of the server.

Disclosed is a system and method for shortening the system management mode when an error occurs in a hardware component in a computer system. The computer system has a hardware component that may have an error. Notification of an error in one of the hardware components is received via the RAS silicon on the processing unit. The error is detected from the hardware component by a system management interrupt handler executed by the boot processor core. Error data is logged into the system error log via a system control interrupt handler executed by the processing unit. During the logging of the error data, the system management mode is avoided. This prevents the system management mode from pausing other processor cores.

This invention relates to a system and method for executing new instructions. The method includes: receiving an instruction; determining whether the received instruction is a new instruction based on its opcode; and when the received instruction is a new instruction: storing basic decoding information of the received instruction into a private register, wherein the basic decoding information includes the opcode; and entering a system management mode, and simulating the execution of the received instruction in the system management mode based on the basic decoding information stored in the private register. Therefore, without modifying the processor's microarchitecture, instructions newly supported by a later-generation processor can be implemented on a previous-generation processor, greatly reducing the workload for design, testing, and other tasks, thus saving significant costs.

The technology describe herein includes upon entering a mode of a processor that is not visible to an operating system (OS), setting a flag indicating entry into the mode and saving an identifier (ID) of an error causing entry into the mode; and responsive to a system reset initiation while in the mode, booting a basic input / output system (BIOS), creating an error record to be accessible to the OS after booting, the error record including the flag and the error ID, and booting the OS.

The invention belongs to the technical field of computers, and discloses a method and a system for printing Debug by a BIOS (Basic Input / Output System) and a computer storage medium, and the method comprises the following steps: storing a generated debugging log into a specified data area of a nonvolatile memory in a firmware running stage of a computer terminal; sending a log reading request to the firmware of the computer terminal through a management interface of the operating system in an operating stage of the operating system; triggering system management interruption based on the log reading request, and enabling a processor to enter a system management mode and execute a log processing program in computer terminal firmware; reading the debugging log from the specified data area by utilizing the log processing program; and returning the debugging log to the operating system through the management interface so as to analyze and present the debugging log in the operating system. According to the method, the BIOS of the Debug version does not need to be recompiled, a serial port debugging line does not need to be connected, the starting-up speed is not influenced, and recurrence analysis of problems is facilitated.

A method for recovering from a legacy operating system environment to a Unified Extensible Firmware Interface (UEFI) preboot environment, comprising: Storing context in the UEFI preboot environment that needs to be preserved under the UEFI preboot environment, wherein the context in the UEFI preboot environment that needs to be preserved comprises a CPU execution context; Restoring an initial portion of the CPU execution context in response to a failure to load the legacy operating system through the UEFI preboot environment; Allowing the CPU associated with the UEFI preboot environment to enter a system management mode and restoring a second section of the CPU execution context under the system management mode; and Exit CPU system management mode and return to the UEFI preboot environment.

The present application relates to a system and method for executing a newly added instruction, the method comprising: receiving an instruction; determining whether the received instruction is a newly added instruction; and when the received instruction is a newly added instruction: generating a simulation identifier, wherein the simulation identifier is a first value; issuing a system management interrupt based on the simulation identifier; entering a system management mode in response to the system management interrupt, and simulating execution of the received instruction in the system management mode to generate a simulation execution result; and storing the simulation execution result in a system management memory. Thus, without modifying the micro-architecture of a processor, a newly added instruction supported by a later generation processor can be implemented on a previous generation processor, thereby greatly reducing the workload for design, testing, etc., and thus saving a large amount of cost.

Various embodiments generally relate to establishing trust in system management mode. An operating system management mode driver can invoke system management mode and provide a signature to the system management mode to utilize the signature to authenticate the driver. Additionally, a hash value of the driver can be used to determine whether the driver is authorized to invoke system management mode or a particular operation or feature of system management mode.

The invention relates to the technical field of computers, and discloses an EC security protection method, computer equipment and a computer readable storage medium. The EC security protection method comprises the following steps: providing an access forbidding list and storing the access forbidding list to a BIOS; when a register access request of the EC is received, triggering the CPU to enter a system management mode, and executing security verification operation in the system management mode: determining a current to-be-accessed target register, and judging whether the target register exists in an access forbidding list or not; and if yes, controlling the EC to exit the configuration mode so as to terminate the current access operation aiming at the target register. According to the embodiment of the invention, the access operation for each register in the access forbidding list can be intercepted from a hardware bottom layer, so that the problem of EC function failure or hardware damage caused by malicious access operation is avoided, and the safety of the EC is improved.