57 results about "Privilege level" patented technology

The invention discloses a debugging system and a debugging method of an RISC-V architecture, and relates to the field of processor debugging, the debugging system comprises a debugging host, a transport layer interface, a debugging module, a debugging logic module in a processor core and a monitoring module, and all the components are in communication connection in sequence. According to the invention, by supporting an RV32 / RV64 double-word-length processor, being compatible with a U / S / M full privilege level operation mode and adapting to various mainstream open-source RISC-V cores and self-defined cores, compared with the existing scheme only supporting a single architecture variant, the method does not need to reconstruct debugging logic for different core types, reduces the core adaptation cost, does not need to customize a debugging instruction or a tool chain process, and has the advantages that the debugging efficiency is improved, and the debugging cost is reduced. Through the register and protocol standardization, the method has high compatibility, and the cross-platform debugging cost is reduced.

A system for securing a large language model (LLM) service against LLM privacy attacks. The system may comprise a processor that executes instructions that cause the processor to: interface with each output of the LLM service and each client network of the LLM service; monitor each output of the LLM to detect at least one client query textual response; detect and redact the at least one client query textual response according to an evaluation of that response and at least one current client privilege level that is assigned to at least one target client network account to which the at least one client query textual response is directed; and transmit a result of the redacting to a client device of the at least one target client network account.

According to examples, an apparatus may include a memory on which is stored machine-readable instructions that may cause a processor to determine, for each of a plurality of members in a group, a respective least privilege level for a resource and determine, based on the determined respective least privilege levels, a privilege level to be assigned to the group for the resource. The instructions may also cause the processor to assign the determined privilege level to the group for the resource and apply the assigned privilege level to the members of the group for the resource.

The invention relates to the technical field of computer security, in particular to an operating system kernel security protection system based on hardware virtualization, which comprises a hardware virtualization module, a kernel isolation module, a security monitoring module and a data protection module. And the system security is obviously improved. Traditional software protection depends on authority management and access control mechanisms of an operating system and is easily subjected to bypassing attacks of malicious programs, for example, protection is broken through by modifying a system call table, utilizing memory vulnerabilities and the like. According to the system, privilege level isolation of hardware virtualization is utilized, a kernel runs in an independent virtual machine with the highest privilege level, a user application program runs in a virtual machine with the low privilege level, and hardware directly prevents unauthorized access of the application program, so that direct attack of malicious codes of an application layer to the kernel is eradicated fundamentally.

An apparatus is disclosed. The apparatus comprises one or more processors to receive a request to trigger a system management interrupt (SMI), execute policy shim code to enforce access control policy in a first privilege level and dispatch the SMI to shield code to enforce the access security policy to perform a system management mode (SMM) and execute the shield code to perform the SMM, including retrieving an operating system (OS) memory preserved warm reset (MPWR) context, saving the context and issuing a warm reset.

A control unit (300) comprising the following: a control unit memory (120) with a configuration register (124) for defining an operating mode of the control unit (300) and a lock register (122) for storing a lock indicator, wherein, immediately after authorization information has been set during a system initialization event, the lock indicator in the lock register (122) is set to a value indicating whether at least part of the authorization information can be changed or not, and set up a controller (302) to: to receive a request for access to a first memory area of ​​a memory (308) from a request device (306) separate from the control unit (300); in response to the request to access authorization information, which contains a multitude of entries corresponding to different memory areas (110-1 to 110-n) of the memory (308), each entry of the multitude of entries comprising a multitude of indicators, the indicators comprising: a first indicator that can assume an active value, representing an execution access mode in which instructions are retrieved from the respective memory area for execution, a second indicator that can assume an active value representing a privileged access mode in which access to the respective memory area is permitted if the requester has a privileged level; and a third indicator representing a read or write mode on a memory area; and Based on the occurrence of the system initialization event and according to the metadata of the request and the authorization information, to determine whether access to the content in the first storage area is allowed.

This application provides a method and apparatus for constructing a permission topology structure based on the lowest privilege level. The method includes: obtaining a non-public interface path template by structured parsing and classifying request data from an identity management platform and performing parameterized substitution; establishing a mapping relationship between the non-public interface path template and a preset identity management platform permission model to obtain a non-public interface parameter structure; merging the non-public interface parameter structure with an existing interface parameter structure to obtain a centralized interface parameter structure; under the lowest privilege role, starting from the initial node of the centralized interface parameter structure according to the task scheduling engine and graph operation model, performing a multi-hop breadth traversal along member relationships, role bindings, and permission operation paths to determine the corresponding permission graph; performing fine-grained dependency extraction on the permission graph; updating the permission graph according to the dependency relationships; and determining the corresponding permission topology structure. This application can improve the security and management efficiency of the identity and access management platform.

According to examples, an apparatus may include a memory on which is stored machine-readable instructions that may cause a processor to determine, for each of a plurality of members in a group, a respective least privilege level for a resource and determine, based on the determined respective least privilege levels, a privilege level to be assigned to the group for the resource. The instructions may also cause the processor to assign the determined privilege level to the group for the resource and apply the assigned privilege level to the members of the group for the resource.

The application relates to a timestamp synchronization method and device across running levels, a chip, a network interface card, equipment, a medium and a program product. The method comprises the following steps: obtaining a first value of a clock cycle count recorded by a system counter since system startup, wherein the same system counter is used by firmware and an application program running at different running levels; in the case that a timestamp synchronization completion flag exists in shared memory, obtaining a second value and a first local timestamp saved by the application program from the shared memory; and obtaining a second local timestamp based on the first value, the second value and the first local timestamp. The method can realize accurate timestamp synchronization of different privilege levels.

To provide a master security device capable of setting operation authority including an access right without a password.SOLUTION: A master security device according to an embodiment comprises an input interface, a memory, a processor, and an output interface. The input interface inputs operator identification information associated with operator device identification information. The memory stores the operator identification information. The processor generates verifiable credentials including an operation permission level including access rights to a client security device and device identification information for the client security device. The output interface outputs the tombstones to the operator device based on the operator identification information.SELECTED DRAWING: Figure 1

The invention relates to a cross-running-level timestamp synchronization method, a cross-running-level timestamp synchronization device, a chip, a network interface card, equipment, a medium and a program product. The method comprises the following steps: acquiring a first value recorded by a system counter and counted by a clock cycle started by a system, and operating firmware and an application program at different operating levels using the same system counter; under the condition that a timestamp synchronization completion mark exists in a shared memory, obtaining a second value and a first local timestamp saved by the application program from the shared memory; and obtaining a second local timestamp based on the first value, the second value and the first local timestamp. By adopting the method, accurate synchronization of timestamps of different privilege levels can be realized.

This invention discloses a design method for a RISC-V AIA interrupt-configurable multi-privilege-level IMSIC controller, comprising: setting a programmable configuration register MS_CUT_CFG in the IMSIC to dynamically allocate interrupt file resources for machine mode (M-mode) and supervisor mode (S-mode) at runtime; controlling the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG to achieve dynamic reuse of interrupt file resources; physically sharing the same hardware register array for the interrupt enable register group (IE) and interrupt suspend register group (IP) of machine mode (M-mode) and supervisor mode (S-mode); and mapping suspended but executable interrupt requests to the corresponding privilege level and submitting them to the processor core through an interrupt arbitration circuit based on the current value of the configuration register. This invention overcomes the limitations of the static resource configuration strategy for IMSIC interrupt files, significantly enhancing the flexibility and dynamic scenario adaptability of RISC-V AIA interrupt applications.

The application provides a lightweight function running method and system for a server-unaware computing scene, and the method comprises the following steps: providing a communication primitive for fast cold start of an isolated environment and high-performance intermediate data transmission; for a server-unaware function computing workflow scene, a runtime is provided as a new software stack architecture; the function and the underlying runtime relied by the function are all deployed in the same CPU privilege level and address space for cold start operation; a library operating system with a workflow granularity is used to provide underlying runtime services for the function, and a memory-safe language is used to provide memory isolation and sharing; and an on-demand loading mechanism is implemented for the library operating system. The application solves the technical problems of slow cold start of an isolated environment, poor intermediate data transmission performance, large cold start range and high cost, and poor flexibility of memory isolation and sharing.

This disclosure provides a virtual machine runtime system, method, processor, and electronic device, relating to the field of virtual machine technology. The system includes: a virtual machine monitor, which runs at a first exception level and is used to create virtual machines using a virtualization environment provided by a microkernel, and to handle interrupt events associated with the virtual machines according to notifications from the microkernel; a virtual machine, which runs at a second exception level; and a microkernel, which runs at a third exception level and is used to provide the necessary virtualization environment for the virtual machine monitor to create the virtual machines, and to intercept interrupt events associated with the virtual machines and notify the virtual machine monitor to handle the interrupt events; the privilege levels of the first exception level, the second exception level, and the third exception level increase sequentially. This disclosure aims to solve the problems of centralized privileges and high resource consumption in existing virtual machine runtime systems.

A processor circuit is configured to receive, while a current software agent is executing in a current execution mode, an indication of an execution mode transition that attempts to change an execution mode index from a current value indicative of the current execution mode to a new value indicative of a new execution mode. The processor circuit is configured to access, based on the current privilege level, particular execution mode transition information in a storage circuit to determine whether the execution mode transition is allowed. The processor circuit is configured to determine, based on particular execution mode transition information, whether to update the current value indicative of the current execution mode. The processor is further configured to update the current value indicative of the current execution mode based on a determination that the execution mode transition is permitted.

The invention relates to a license translator. Systems, methods, and circuitry are provided for translating permission identifiers in bus access transactions. In one example, a processing system includes a source system element characterized by a plurality of source privilege levels; a destination system element characterized by a plurality of destination privilege levels; and translator circuitry coupled between the source system element and the destination system element. The translation circuitry includes an input and an output. The input is coupled to a source system element that inputs a bus access transaction, where the bus access transaction includes a source permission identifier that indicates a source privilege level. The output is coupled to a destination system element. The output provides a modified bus access transaction in which the source permission identifier is replaced by a destination permission identifier indicating a destination privilege level mapped to the source privilege level.

Systems, methods, and circuitries are provided for translating permission identifiers in bus access transactions. In one example, a processing system includes a source system element characterized by a plurality of source privilege levels; a destination system element characterized by a plurality of destination privilege levels; and translator circuitry coupled between the source system element and the destination system element. The translation circuitry includes an input and an output. The input is coupled to the source system element that inputs a bus access transaction, where the bus access transaction includes a source permission identifier indicating a source privilege level. The output coupled is to the destination system element. The output provides a modified bus access transaction in which the source permission identifier is replaced with a destination permission identifier indicating a destination privilege level mapped to the source privilege level.

Apparatuses, methods, computer programs and computer readable storage media are provided. Data processing occurs at a current privilege level of multiple privilege levels and when an exception coercion flag for the current privilege level is set, any instruction is responded to by taking a specified type of exception to an exception handling privilege level. The exception coercion flag for the current privilege level cannot be set when operating at the current privilege level other than by an exception return to the current exception level, and the exception coercion flag for a less privileged level can be set when operating in a more privileged level of the multiple privilege levels. When switching from operating at the current privilege level to a target privilege level, the exception coercion flag for the target privilege level is cleared.

The embodiment of the invention provides a configuration method of an input / output memory management unit, electronic equipment and a storage medium, and the configuration method of the input / output memory management unit comprises the following steps: responding to an access request of a virtual machine to a virtual input / output memory management unit; the access request exits from the virtual machine to a kernel mode of a first privilege level, and the virtual input / output memory management unit runs in the kernel mode of the first privilege level; the virtual input / output memory management unit reads configuration information from the memory of the virtual machine according to the access request, and generates a simulation configuration result according to the configuration information; and the virtual input / output memory management unit configures the input / output memory management unit according to the simulation configuration result. According to the scheme, the efficiency of configuring the input / output memory management unit can be improved.

A system is disclosed for Input / Output (I / O) device emulation that allows a service provider to configure and enforce a policy for software access to some or all I / O resources in a platform. I / O device emulation enables service providers to protect their platforms from malicious guest software that may be executed on associated platforms that has direct access to I / O resources in case of bare-metal servers, escalates the privilege level from guest to host in case of hosted-Virtual Machine servers, or escalates the privilege level from guest to System Management Mode in case of either bare-metal servers or hosted-Virtual Machine servers. The technology enables service providers to protect their platforms from malicious guest software running on their platforms that either has direct access to legacy I / O and memory mapped I / O resources. In one illustrative example, the platform may include a microprocessor.

An arrangement and a method of privilege escalation detection in a computer or computer network. The method comprises examining which executables are running in a target host; searching from a behavioral data source behavioral information of the executables running in the target host; including in a first list identification information of executables running in the target host which the behavioral information indicates are known to run with a first or a higher level privilege; including in a second list identification information of sensitive resources loaded or executed by the executables included in the first list; examining the sensitive resources included in the second list to determine whether that resource is writable by an executable running at a privilege level lower than the first level; and providing an indication of every resource that is loaded by the first or higher level privilege executable but is writable by the executable running at a privilege level lower than the first level as a potential vulnerability.

A method of executing a security critical application (150) on a hardware platform (100) is presented. The method comprises: executing a virtual machine monitoring program (120) having a monitoring component (130) for a security critical application (150) on a hardware platform (100); instantiating at least one virtual machine (140) by a privilege level of the virtual machine monitoring program (120) hardware platform that is lower than the privilege level of the virtual machine monitoring program (120); a list of one or more predefined actions is provided that, when executed by the processor core (112a, 112b), have relevance to the integrity and / or operation of the safety critical application (150). The method further comprises instructing, by the virtual machine monitoring program (120), the processor core (112a, 112b) to divert the control flow towards a respective handler (132) in the monitoring component (130) for the action to be performed when the action to be performed is about to be performed on the list; and executing at least the security critical application (150) over the guest operating system (142) in the at least one virtual machine (140). Further, a check of whether the action is allowed or not allowed may be performed, and / or at least one preparation for the action to be performed may be performed.

A system call method and device, the method comprising: a kernel of a first virtual machine receiving an interrupt instruction of a first process, the first process running in a user space of a second virtual machine, the kernel of the first virtual machine running in a kernel space of the second virtual machine, the second virtual machine being configured to provide a running environment of the first virtual machine, at this time, a CPU switching from a user state to a kernel state; the kernel of the first virtual machine mapping a first address associated with the interrupt instruction to a second address, the kernel of the first virtual machine executing the interrupt instruction based on the second address, obtaining an interrupt processing result, and sending the interrupt processing result to the first process, at this time, the CPU switching from the kernel state to the user state. Therefore, in the process of the first virtual machine calling the system, the CPU only needs to switch between the kernel state and the user state twice, thereby reducing the privilege level overhead, the context switching overhead, and the resource consumption of the CPU.

A system is disclosed for Input / Output (I / O) device emulation that allows a service provider to configure and enforce a policy for software access to some or all I / O resources in a platform. I / O device emulation enables service providers to protect their platforms from malicious guest software that may be executed on associated platforms that has direct access to I / O resources in case of bare-metal servers, escalates the privilege level from guest to host in case of hosted-Virtual Machine servers, or escalates the privilege level from guest to System Management Mode in case of either bare-metal servers or hosted-Virtual Machine servers. The technology enables service providers to protect their platforms from malicious guest software running on their platforms that either has direct access to legacy I / O and memory mapped I / O resources. In one illustrative example, the platform may include a microprocessor.

The application provides a permission domain management method and system for a multi-privilege-level processor resource, which comprises the following steps: an instruction verification step, a register read-write verification step, a register bit field write verification step, and a start initialization step; the start initialization step is performed according to an ISA-Context, and the ID of a current permission domain is obtained; the instruction verification step is performed according to the ID of the current permission domain; the register read-write verification step is performed according to the ID of the current permission domain; and the register bit field write verification step is performed according to the ID of the current permission domain. The application uses permission domains to isolate the processor resources, that is, multiple permission domains, specifically 256 permission domains, exist, and the resources are isolated in the granularity of a single instruction or a register bit field in each permission domain, so that the granularity of the processor resource permission isolation is finer.

The invention relates to the technical field of virtual machines, and particularly discloses a HyperVHE virtual machine system based on a ZVM, which runs on an ARM processor and comprises a host operating system running at an EL2 privilege level; the ZVM runs at an EL2 privilege level, cooperatively runs with the host operating system at the same level, shares control authority, and realizes distribution and management of resources and interrupts through a predefined interface; the at least one guest operating system runs at an EL1 privilege level, and access control, memory isolation and interrupt forwarding of the guest operating system are taken over by the ZVM; wherein the kernel of the host operating system is subjected to EL2 privilege level transformation. By adopting the technical scheme of the invention, the system can run in an ARMv8.0 architecture, and has the advantages of higher real-time performance and light weight.

A method and system for kernel data isolation based on multiple kernel page tables is provided. Through creating multiple kernel page tables in a kernel system and binding specific applications to a corresponding page table for operation, each internal process of the application remains consistent with the corresponding page table in terms of kernel address space, and the kernel address spaces of different applications are isolated from each other due to existence of the different page tables. The system includes a page table management module and a private memory management module. The present disclosure protects private application data at the granularity of applications in the same kernel at very low costs to prevent data breach caused by read attacks on kernel address space or privilege escalation attacks, maintains privilege level division of kernel address spaces, and ensures transparency of private memories among applications and general IO capability of private memories.

This invention proposes a hardware-assisted isolated execution method for eBPF programs, comprising: acquiring the eBPF program to be executed; setting all data pages accessed in the eBPF program to non-privileged pages; issuing all memory access instructions in the eBPF program as non-privileged access instructions through just-in-time (JIT) compilation to obtain the program to be executed; running the program to be executed in kernel mode EL1 of the server operating system to obtain the execution result; and during the execution of the program to be executed, the non-memory access instructions in the program to be executed run at the kernel mode EL1 privilege level, and the memory access instructions in the program to be executed are non-privileged access instructions, which are run at the user mode EL0 non-privileged level. By setting the memory of the eBPF program to non-privileged pages, the eBPF program still runs at a privileged level, but is issued with non-privileged memory access instructions. Since the kernel memory is set to privileged pages, the eBPF program cannot access them, thereby ensuring kernel memory safety.

An apparatus, method and system to implement a mechanism to limit out-of-compliance intra-die communication. A receiver receives a packet directed to a component on a die or a package containing the die. A logic circuit evaluates attributes of the packet based on a number of criteria and a privilege level associated with the component that is a target of the packet, wherein the logic circuit is to: when the attributes of the packet meet the number of criteria, evaluate a packet privilege level to access the component to the privilege level associated with the component and grant, substitute or downgrade the packet privilege level to access the component; and when one or more attributes of the packet does not meet the number of criteria, reject the packet.

A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.