87 results about "FeiTeng" patented technology

The invention discloses an industrial PCB cooperative control method based on open-source and Feiteng CPUs, particularly relates to the technical field of industrial automatic production line control, and is used for solving the problem that a quality control instruction and a board card physical flow in an existing PCB production line are difficult to accurately synchronize, so that an adjustment instruction is lagged or mistakenly acted. A unique identifier is generated for each printed circuit board, the position of each printed circuit board is tracked in real time, and when a board card enters a synchronous control area, a Feiteng CPU obtains the state of each execution device; selecting a data query strategy based on state consistency, and collecting node state feedback and quality data; according to the method, the consensus convergence rate and the phase-frequency characteristic distortion index of the system are calculated, the triggering time point of a control instruction is dynamically adjusted when the index is abnormal, and a correction instruction is sent to execution equipment through an open source gap distributed soft bus, so that high-precision cooperative control of the instruction and board card flow is realized, and the real-time performance and reliability of closed-loop quality control are improved.

The invention relates to the technical field of unmanned aerial vehicle safety, in particular to an unmanned control system dynamic key trust chain construction method based on a Feiteng E2000TCM, and the method comprises the steps: generating a hardware root key which cannot be exported through the TCM of Feiteng E2000TCM, and enabling the hardware root key to serve as a starting point of a whole trust chain; after the flight control system of the unmanned aerial vehicle is electrified, started and initialized, based on the hardware root key and the equipment unique identification code of the flight control system, deriving a system key by using a Hash algorithm; after the unmanned aerial vehicle takes off, deriving a task key by using a hash algorithm based on the system key and the identifier of the current flight stage; when the unmanned aerial vehicle needs to communicate with a ground station or other unmanned aerial vehicles in the current flight stage, based on the task key and the environmental risk level corresponding to the current flight stage, an interaction key is derived by using a Hash algorithm. According to the method, a data communication dynamic trust security protection mechanism of the flight control system of the unmanned aerial vehicle is realized, and malicious threats and viruses can be effectively defended.

The invention provides a multi-voltage adapter compatible method and system based on Feiteng D3000 and a medium, and the method comprises the steps: firstly, generating a first switch control signal based on a preset voltage threshold comparison logic according to first voltage information inputted by an adapter; then, according to the first switch control signal, a corresponding power supply path is switched on, second voltage information is obtained, and for the second power supply path, a first voltage regulation parameter is configured based on preset voltage regulation logic, and second voltage information is obtained; and finally, on the basis of a preset confidence degree setting logic, first confidence degree information is obtained according to the second voltage information and is used for judging and triggering a redundancy protection mechanism. According to the invention, the compatibility problem of the product is solved through voltage detection and logic decision, multiple protection is formed through dynamic voltage regulation and redundancy protection, and the reliability and safety of the product are improved.

The invention relates to a method and system for realizing a Power Loss control function based on a Feiteng CPU, and the method comprises the steps: adding a code in a BIOS to realize the communication between the BIOS and an MCU, and transmitting Power Loss strategies, such as Power Off, Power On and Last State parameters, set in the BIOS by a user, and an instruction sent to the MCU by the BIOS under the condition of normal shutdown to the MCU through an I2C bus; an MCU firmware program is developed, so that the MCU can communicate with a BIOS, can store related instructions sent by the BIOS, can judge the access and removal of an AC power supply, and can control whether a computer is automatically powered on or started up according to a Power Loss strategy set by a user after the AC power supply is accessed; the power Loss control function of the Feiteng computer is achieved through mutual cooperation of the MCU and the BIOS, and the industrial problem that a current computer applying a Feiteng CPU does not support the power Loss control function is solved.

The invention provides a trusted startup system and a startup method of the trusted startup system, and belongs to the technical field of communication, the system comprises an on-chip ROM (Read Only Memory) located in a CPU (Central Processing Unit), a one-time programmable memory located in the CPU, a password acceleration engine located in the CPU and an FPGA (Field Programmable Gate Array) chip connected with the CPU, the system comprises an FPGA (Field Programmable Gate Array) chip, a startup firmware chip, a system file chip and a system file backup chip which are connected with the FPGA chip, an on-chip boot program stored in an on-chip ROM (Read Only Memory), a trusted password module stored on a password acceleration engine, and Feiteng basic firmware, Feiteng universal firmware and a trusted system which are stored in startup firmware, and the self-developed Linux system is stored in the system file and the system file backup. According to the method, the system and the system starting process are completely credible, including security, credibility and tamper-proofing of all files in the system starting operation process, and security starting and tamper-proofing of the system are ensured in a mode of combining software design and hardware design.

The invention relates to the technical field of clock source sharing, and particularly discloses a system and a method for sharing a clock source by a platform, which are used for sampling LVPECL clock signals distributed to a Feiteng processor and a 10-gigabit network card by a clock buffer so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; and a signal processing algorithm based on artificial intelligence and deep learning is introduced at a rear end to analyze LVPECL clock sampling signals of the two, so that fine-grained optimal matching interaction characteristics of the LVPECL clock sampling signals of the two are learned and captured, and signal waveform semantic joint representation and clock buffer performance monitoring are carried out. Therefore, the monitoring result of whether the working state of the clock buffer is abnormal or not is obtained. Therefore, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring mode, and the working condition of the clock buffer can be fed back in time.

The embodiment of the invention relates to the technical field of communication, in particular to a FLASH extended space read-write access method based on a domestic Feiteng E2000Q processor, which comprises the following steps of: in the aspect of hardware, respectively hanging a plurality of FLASH chips in different chip selection spaces of a QSPI (Query Serial Peripheral Interface) controller of the domestic Feiteng E2000Q processor, providing clock signals for each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through the FPGA, and a standard library is formed; in the aspect of software, when FLASH erasing, reading or programming operation needs to be carried out, selection of different FLASH chips is achieved in the mode that FLASH chip selection parameters are transmitted to a chip selection register of the QSPI controller, and read-write access operation is achieved in the mode that FLASH addresses are transmitted to an address register of the QSPI controller. Read-write operation of the high-order data and the low-order data in the same address space is achieved in a data splicing and analyzing mode. According to the method, the flexibility of the domestic Feiteng E2000Q processor in the aspects of application program solidification and FLASH address space allocation is well improved.

The invention discloses an MAC (Media Access Control) address configuration method, which is applied to a Feiteng processor platform, and the Feiteng processor platform comprises a Feiteng processor, an EEPROM (Electrically Erasable Programmable Read-Only Memory) and UEFI firmware. The method comprises the following steps: writing a target MAC address into a specific storage position of an EEPROM; and the UEFI firmware reads the MAC address from the specific storage position of the EEPROM in the DXE stage, and writes the MAC address into the MAC address register of the Feiteng processor network controller. According to the invention, the persistent configuration of the MAC address can be realized.

The invention relates to the technical field of block chain technology and education data management, and discloses an education data management system and method based on a block chain, and the method comprises the steps: constructing an education business field specific language, and training an education business intention understanding model; applying a constraint solving algorithm to solve the smart contract parameters meeting various constraint conditions, and generating a smart contract code meeting multi-objective optimization; performing multi-level formalized verification on the generated intelligent contract code; constructing an educational policy and regulation knowledge base and calculating a contract policy compliance score; implementing a hierarchical transition strategy; the system is constructed based on a domestic Feiteng processor and a Kylin operating system, and stable operation and data security in an extreme environment are ensured; the technical problems of difficulty in intelligent contract development, difficulty in policy compliance evaluation and complexity in contract evolution upgrading in education data management are solved, and reliable storage, safe sharing and effective management of education data are realized.

The invention belongs to the technical field of intelligent management and control of indirect cooling and air cooling systems, and discloses a localized adaptive indirect cooling and air cooling intelligent management and control integrated system. Comprising a localized hardware platform, a localized software platform, a mobile robot subsystem, an infrared temperature measurement and intelligent detection subsystem, an intelligent treatment subsystem, an upper and lower double-drive control subsystem, a flexible drag chain subsystem and an intelligent management and control centralized control center subsystem. The domestic hardware platform adopts domestic mainstream CPUs (Central Processing Unit), including Peng, Haiguang, Feiteng, Loongson, Mega-Core and SW, the dominant frequency is not lower than 2.3 GHz, the number of cores is not less than 4, and comprehensive domestic adaptation is realized: the domestic mainstream CPUs, electrical equipment and sensors are adopted in hardware of the system, and a domestic operating system, a database and middleware are adopted in software of the system; comprehensive localization adaptation from a bottom layer to an application layer is achieved, dependence on imported technologies is reduced, data safety and system stability are guaranteed, and national information and credential requirements are met.

The utility model discloses a double-guide-rail type multi-extension server based on a Feiteng D2000 platform. The double-guide-rail type multi-extension server comprises a box body, a mainboard, an upper-layer extension module, a lower-layer extension module, a first guide rail assembly, a second guide rail assembly, a hard disk and a power supply, the first guide rail assembly comprises a first guide rail and a first bracket, the first guide rail is connected with equipment, the first bracket is arranged on the box body, and the first bracket is connected to the first guide rail in a front-back sliding mode; the second guide rail assembly comprises a second guide rail and a second bracket, the second guide rail is arranged in the box body, the second bracket is connected to the second guide rail in a front-back sliding mode, and the lower-layer expansion module is arranged on the second bracket; thus, the first guide rail assembly is utilized to enable the box body to be arranged on the equipment in a pluggable mode, and the second guide rail assembly is matched to achieve the effect that the lower-layer expansion module is arranged on the box body in a pluggable mode, so that disassembly and assembly of the upper-layer expansion module and the lower-layer expansion module on the box body are facilitated, follow-up maintenance and replacement are facilitated, the working efficiency of a server is improved, and the application range is wide.

The present invention discloses a hardware anti-copy board circuit for a Feiteng processor, comprising a temperature sensor module, a CPLD circuit module, a Feiteng processor module, and a UEFI firmware module. The temperature sensor module, the CPLD circuit module, the Feiteng processor module, and the UEFI firmware module are sequentially connected. The temperature sensor module includes two 8-bit user-readable and writable registers for recording a power-on secret message. The CPLD circuit module is used to read the register data and is controlled by the ACPI power control pins PWR_CTL0 and PWR_CTL1 of the Feiteng processor. Based on the control of these two pins of the Feiteng processor, the CPLD determines whether to generate a reset signal RST to the Feiteng processor. The advantages of the present invention are that the temperature sensor module is used as a memory for the power-on secret message, and the CPLD program is stored internally on the chip, making it extremely difficult to crack the program. Therefore, through multiple encryption methods, the present invention can achieve the purpose of anti-copy board for Feiteng processors.

The utility model provides a cooling fan automatic control circuit used for a domestic Feiteng CPU, which comprises a cooling fan speed regulation main control circuit and a cooling fan driving circuit, a temperature sensor and a fan speed regulation communication support module are arranged in the domestic Feiteng CPU, an input end of the cooling fan speed regulation main control circuit is connected with the temperature sensor, and an output end of the cooling fan speed regulation main control circuit is connected with the fan speed regulation communication support module. The cooling fan speed regulation main control circuit is in communication connection with the fan speed regulation communication support module, the cooling fan speed regulation main control circuit is connected with the cooling fan driving circuit, and the output end of the cooling fan driving circuit is connected with the CPU cooling fan. The cooling fan speed regulation main control circuit can control the cooling fan driving circuit to adjust the rotating speed of the CPU cooling fan according to temperature information fed back by the temperature sensor and temperature control curve information provided by the fan speed regulation communication support module. The utility model has the beneficial effects that the temperature of the CPU can be acquired in real time and the running speed of the cooling fan can be adjusted.

The utility model discloses a 3U CPCI (Compact Peripheral Component Interconnect) blade computer mainboard based on a Feiteng processor, which comprises a CPCI mainboard, and cutting structures are arranged at the edges of PCB (Printed Circuit Board) guide rails on two sides of the CPCI mainboard; when the CPCI mainboard is used as an air cooling mainboard, the PCB guide rail edges on the two sides of the CPCI mainboard are in sliding fit with the air cooling case track; when the main board is used as a cold conduction main board, the main board is matched with the fixed installation mode of a cold conduction case by removing the PCB guide rail edges. According to the CPCI mainboard, the cutting structures are arranged on the edges of the PCB guide rails on the two sides of the CPCI mainboard, so that the CPCI mainboard can be flexibly matched with different types of cases; no matter a 4HP air cooling case or a cold conduction case, seamless installation and compatibility can be achieved through a corresponding cutting structure, the adaptability and universality of the mainboard are remarkably improved, and application scenes with different heat dissipation requirements are met.

The present application provides a ladder diagram program application device and method. The ladder diagram program application device provided by the present application is applied to the Feiteng platform, and the ladder diagram program application device at least includes a host computer; the host computer is used to build a target project file on the Feiteng platform based on the ladder diagram library, and the target project file includes at least one ladder diagram, and the host computer at least includes a ladder diagram library; the host computer also includes at least a compilation module, which is used to compile the target project file according to the Feiteng platform instruction set. The ladder diagram program application device and method provided by the present application, on the one hand, by abstracting the ladder diagram into a unified and standardized variable table file and a universal form of a processing logic file, the ladder diagram files of different platforms are integrated on the Feiteng platform, and the ladder diagram can be freely transferred and processed between multiple platforms, with good reusability and low time cost for ladder diagram transplantation; on the other hand, PLC programming is realized through ladder diagrams on the Feiteng platform.

The invention discloses a multi-task modular hierarchical regulation and control system based on a multi-core CPU architecture, which relates to the technical field of power generation control, and comprises a domestic multi-core CPU hardware basic module adopting a Feiteng or Peng architecture, a triple modular redundancy design and a 24-bit AD signal acquisition module based on a domestic operating system; the multi-task hierarchical scheduling core module is used for five-level priority division, a core binding and dynamic migration strategy and an improved round-robin algorithm; the modular function adaptation interface module supports hot plug, parameter self-matching and dual-path redundancy switching; the running state monitoring and feedback module is used for evaluating the health state in a weighted fusion manner; and an open development support module, dual-mode configuration and an encapsulation algorithm support third-party development and version management. According to the method, DCS autonomous controllability and efficient and balanced multi-task scheduling are realized, the operation monitoring and operation and maintenance intelligent level is improved, and safe and efficient operation of a unit is guaranteed.

The utility model discloses a Feiteng FT2000 main control computer and power-on self-starting circuit, the power-on self-starting circuit includes RC circuit, Schmitt trigger and MOS switch, the RC circuit includes first RC circuit and second RC circuit that are connected in parallel, the first RC circuit includes first resistor and first capacitor that are connected in series, and the second RC circuit includes second resistor and second capacitor that are connected in series. The first RC circuit comprises a first resistor and a first capacitor which are connected in series, the second RC circuit comprises a second resistor and a second capacitor which are connected in series, the Schmitt triggers comprise a first Schmitt trigger and a second Schmitt trigger, the MOS switches comprise a first MOS switch and a second MOS switch, and the first Schmitt trigger and the second Schmitt trigger are respectively connected in series to the first RC circuit and the second RC circuit. The first MOS switch is connected to the second RC circuit in series, the second MOS switch is connected between the RC circuit and a PWRBTNEN pin of the FT2000 processor in series, the resistance value of the first resistor is larger than that of the second resistor, and the design cost of the self-starting circuit can be greatly saved.

According to the application, a computer power management control system and method based on FT2000 processor are provided, which comprises: a computer power management control module: based on FT2000 notebook, according to the requirement of different states of the computer to the power, the power-on and power-off timing of each power supply is controlled by domestic CPLD, so as to realize the computer power management control; a charging and temperature control module: communicating with the single-chip microcomputer, CPLD and FT2000 through IIC interface, so as to realize the battery charging management function, notebook temperature detection and heat dissipation function.

The utility model relates to control management module technical field, concretely relates to a 3UVPX control management module based on Feiteng E2000S, this module takes Feiteng tenglong E2000S CPU as the core, adopts specific package form, possesses advanced characteristic and rich integration function. Network design adopts WX1860AL4 and XPHY0111QFIGR combination, realizes gigabit ethernet interface function. Through leading out two way I2C as IPMB, combine chassis management unit ChMC and board card management unit IPMC, follow IPMI2.0 agreement, realize the collection and control to each module state information in chassis. The module high integration, the performance is superior, can effectively satisfy the multiple needs of rugged chassis management.

The invention discloses a satellite-borne computer device based on a D2000V processor, and belongs to the technical field of satellites. Comprising a processor module, a control module, a storage module, a power module and an external interface module. The processor module adopts a Feiteng D2000V processor to form a minimum hardware system for CPU (Central Processing Unit) operation of the processor; the control module adopts an anti-fuse type or Flash type FPGA (Field Programmable Gate Array) to realize a control management function, and mainly comprises health management functions such as remote control and telemetering information processing, program reconstruction management function, storage channel selection, CPU (Central Processing Unit) start control, CPU on-orbit operation state management, fault diagnosis and the like; the storage module realizes a program storage function of the processor and adopts a multi-redundancy physical backup form, the power supply module realizes input power supply conversion and provides a basic power supply function for the spaceborne computer device, and the external interface module realizes external information interaction of the spaceborne computer device. The reconstruction scheme is flexible, the integration level is high, external interfaces are rich, the space environment adaptability is high, and various satellite processing load requirements are met.

The utility model discloses a computing server based on a Feiteng S5000C-32 computing blade, which comprises a processor unit, and the processor unit is electrically connected with a BMC (Baseboard Management Controller) health management unit, a 40G network card unit, a front-out gigabit network card unit, a rear-out gigabit network card unit, a display unit, a serial port unit, a USB (Universal Serial Bus) / SATA (Serial Advanced Technology Attachment) interface unit, an IPMB (Intelligent Platform Management Bus) interface unit, a hot plug unit and a clock unit. A domestic Fengyun S5000C-32 core processor is used as a core, front-end data comprehensive processing is completed, and operation resource support is provided for achieving functions such as task management, system management, data fusion, comprehensive detection and comprehensive recognition. The processor can provide PCIE5.0, DDR5, a debugging serial port and other interfaces to the outside, the application scenarios of radar signal processing, data processing and the like needing high-speed intensive calculation can be met, and the module adopts a chip produced in China, so that the international competitiveness of the product is improved.

The invention discloses a multi-type data high-speed interaction method based on Feiteng D2000 and an FPGA (Field Programmable Gate Array), which comprises the following steps of: acquiring the total number of FPGA chips on a PCI (Peripheral Component Interconnect) bus under an operating system directory, traversing all the FPGA chips to finish initialization, performing partition processing on DDR (Double Data Rate) mounted on each FPGA, performing address mapping on a Bar space, storing flag bit information related to uplink and downlink data, and storing the flag bit information related to the uplink and downlink data. The application program creates a thread polling Bar space flag bit to obtain a data updating state, the number and the position of unread data are obtained through calculation, and a driving function is called to read the data and forward the data. The data sending step comprises the steps of mapping according to a destination chip name to obtain an equipment descriptor, packaging a message header, judging whether to carry out zero filling operation or not to obtain final sending data, and subpackaging and calling a driving function to send the data according to an agreed fixed byte. Therefore, the purpose of multi-type data high-speed interaction between the Feiteng D2000 and the FPGA is achieved.

The application discloses a dual-time system communication method and system based on a Feiteng Kirin platform and a CPLD, and the dual-time system communication method comprises the following steps: acquiring a generation source of a time system source; judging the type of the time system source according to the acquired generation source of the time system source; and controlling the CPLD by the CPU in the corresponding time system source mode according to the judged type of the time system source, so as to realize the control of the time system source. The dual-time system communication method and system based on the Feiteng Kirin platform and the CPLD have the advantages that the CPU and the CPLD are adopted, the manufacturing cost is low, the occupied space is small, the degree of intelligence is high, and the user is convenient to use.

The embodiment of the invention discloses a resolution adaptation method and device based on Feiteng E2000 external equipment, a terminal and a medium, and the method comprises the steps: obtaining a resolution list of the external HDMI equipment when a Feiteng E2000 notebook computer is externally connected with the HDMI equipment; judging whether the resolution supported by the Feiteng E2000 notebook computer is matched with the resolution of the external HDMI equipment or not; if not, adding a virtual resolution parameter adaptive to the external HDMI device in a GPU drive of the Feiteng E2000 notebook computer; initializing GPU display output configuration to enable the GPU to process display data according to the virtual resolution parameter; and transmitting the processed display data to the external HDMI interface through a transmission channel of the external HDMI equipment. And therefore, the external HDMI equipment can normally display according to the resolution of the external HDMI equipment.

The present invention discloses a software-based frequency domain matched filtering method based on the VSIPL standard. The method comprises the following steps: initializing a VSIPL library, binding a complex block object to a user data array, and binding a matrix view to the complex block object to convert the complex block object into a permitted state; calling a vsip_ccfftmop_create_f function to create a pointer to a one-dimensional multi-FFT object; performing a fast Fourier transform on a radar echo matrix using the vsip_ccfftmop_f function to obtain first data transformed into a frequency domain; calling a vsip_fftm_destroy_f function to destroy the one-dimensional multi-FFT object; cyclically calling a vsip_cvmul_f function to multiply Nrfft data points in each row of the first data by a matched filtering coefficient to obtain second data; and calling a vsip_ccfftmop_create_f function, a vsip_ccfftmop_f function, and a vsip_fftm_destroy_f function to convert the second data into a time domain to obtain a matched filtering result. The present invention not only ensures the portability of the program, but also improves the operating efficiency of the VSIPL middleware on the Feiteng platform.

The application provides a system, method and device for clearing CMOS settings on a domestic Feiteng platform, belonging to the technical field of CMOS setting clearing, and the system comprises an MCU, a BMC, a CPU, a first Flash chip, a second Flash chip, a button cell and a server mainboard power supply; the CPU is connected with a first chip selection switch, and the first chip selection switch is connected with the first Flash chip, the second Flash chip and the MCU; the BMC is connected with a second chip selection switch, and the second chip selection switch is connected with the first Flash chip and the second Flash chip; the MCU is connected with the button cell, the server mainboard power supply and the BMC, and the MCU is further connected with a power-on button and a short-circuit PIN. In the case of AC power failure, the application restores the factory settings of the BIOS firmware through the backup Flash chip, reduces the risk of human operation, reduces the loss, and improves the maintenance convenience.

This invention discloses a dynamic partial reconfiguration method based on a DSP chip. During DSP operation, this method receives external commands and data through a peripheral interface and updates the relevant data of the function to be reconfigured in the application program to complete the partial reconfiguration. This method does not require powering down or restarting the application program, and does not affect other modules in the program. This method uses functions called in the application program as the elements for partial reconfiguration, and uses the TI TMS320C6678 multi-core DSP chip as the hardware carrier. The effectiveness of this method has been verified, and the domestic Feiteng FT-M6678 is also applicable.

The invention belongs to the technical field of servers, and particularly discloses a multi-path Feiteng CPU cascade management system applied to a server. The system comprises a microcontroller unit and a programmable logic unit, the microcontroller unit is connected with each CPU and used for monitoring output information of each CPU in real time, if fault information is analyzed from the output information, the fault CPU is isolated, and the cascade mode of the CPU is switched; the switching module is also used for switching the cascade mode of the CPU according to the cascade mode switching command; the microcontroller unit is also connected with a server power supply, and the power supply output of the server power supply to each CPU is adjusted according to the cascade mode of the CPUs; and the programmable logic unit is connected with the microcontroller unit and is used for adjusting the power-on time sequence of each CPU according to the cascade mode of the CPU selected by the microcontroller unit. By means of the system, online switching of the multi-channel Feiteng CPU cascade mode is achieved.

The invention relates to a miniaturized low-power-consumption processor board, and belongs to the technical field of signal processing systems. The processor board takes Feiteng D2000 / 8 as a core, and can realize functions of display, control, storage, external data interface and the like; and the processor board comprises a Feiteng D2000 / 8 processor, a Feiteng bridge chip X100, a BMC (Baseboard Management Controller) and onboard DDR4 particles. The Feiteng CPU, the memory, the network, the serial port and other chips are integrated, more interfaces are reserved on the mainboard, the functions of display, control, storage, external data transmission and the like can be achieved, and the performance requirements in complex application scenes can be met.

The invention discloses a detection device and method for a Feiteng S5000C processor, a complete intelligent detection system is constructed by integrating a processor clamp, a voltage and current detection module, a temperature monitoring module, an MCU control module and a man-machine interaction module, and real-time data acquisition, multi-dimensional performance evaluation and intelligent grading judgment algorithms are adopted. Accurate testing and automatic grading of the power consumption characteristic and the temperature tolerance of the Feiteng S5000C processor are achieved. The detection device provides an intuitive man-machine interaction interface, and breaks through the limitation that a traditional detection scheme depends on PC terminal control, lacks field real-time display and is prone to errors in manual recording.