Satellite-borne computer device based on D2000V processor
By adopting the D2000V processor and multiple redundant memory design, combined with FPGA control module and ECC error correction function, the problems of insufficient computing performance and space environment adaptability of spaceborne computers were solved, realizing a high-performance, low-cost and high-reliability spaceborne computer device.
Patent Information
- Application Number
- CN202610131700.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional spaceborne computers have insufficient computing power to meet the needs of satellite payload missions, and are prone to single-event upsets and failures in the space environment, leading to abnormal startup. Expensive aerospace-grade radiation-hardened devices cannot meet the requirements of low-cost design.
Employing a high-performance D2000V processor, combined with a multi-redundant memory design and antifuse or Flash FPGA control modules, it enables program backup and reconstruction, enhances adaptability to the space environment, and utilizes ECC error correction and multi-channel memory, along with a rich array of external interfaces, to achieve high reliability and low cost.
It improves the computing performance of onboard computers, enhances reliability in the space environment, reduces failure rate and cost, adapts to various satellite processing payloads, and has high integration and rich interface compatibility.
Smart Images
Figure CN122019462A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a spaceborne computer device based on a D2000V processor, belonging to the field of satellite technology, and is particularly suitable for high-performance computing, high reliability, and low-cost spaceborne devices. Background Technology
[0002] As the control, computing, and data processing hub of a satellite payload, the onboard computer undertakes core tasks such as payload management and data processing. Its performance and reliability directly determine the success or failure of the satellite payload mission. With increasing demands on satellite payload missions, the computational performance requirements are constantly rising, and traditional onboard computers are insufficient to meet mission needs. Furthermore, high-energy particles in the space environment can easily cause processor failures such as single-event upsets and single-event lockouts. The harsh space environment can also easily cause onboard computers to fail to start normally or malfunction during startup. Traditional satellite payloads use expensive aerospace-grade radiation-hardened devices, which cannot meet the low-cost design requirements of the satellite internet industry. Therefore, it is necessary to design a highly reliable, space-environment-adaptable, high-performance, and low-cost onboard computer device to address both the insufficient computational performance problem and enhance environmental adaptability, reducing the impact of space radiation and lowering the on-orbit failure rate. Summary of the Invention
[0003] To address the problems existing in the aforementioned background technology, this invention provides a spaceborne computer device based on the D2000V processor. This invention solves the problem of insufficient computing performance of traditional spaceborne computers, improves the computing power of payload products, enhances adaptability to the space environment, and meets the requirements of radiation-resistant, high-performance, and low-cost spaceborne computers.
[0004] The technical solution of this invention is implemented as follows:
[0005] A spaceborne computer device based on a D2000V processor includes a processor module 1, a control module 2, a storage module 3, a power supply module 4, and an external interface module 5.
[0006] The processor module 1 mainly includes a Phytium D2000V processor, DDR4 memory, clock, external debugging network port and serial port, etc., forming the minimum hardware system for the processor CPU to run.
[0007] Among them, the control module 2 realizes remote control and telemetry information processing, program refactoring management, storage channel selection, CPU startup control, CPU on-orbit operation status management, fault diagnosis and other health management functions.
[0008] Among them, storage module 3 implements the processor's program storage function. The program storage is divided into boot memory, system and application memory. The memory type adopts SPI interface form Nor Flash memory and adopts multiple redundancy physical backup form. First, it realizes multiple program backups during on-orbit operation. Second, it designs multiple memory chips to achieve triple redundancy, enhances the adaptability of the space environment during processor startup, and can effectively prevent processor startup problems caused by single event faults, with high reliability characteristics.
[0009] Among them, the power module 4 realizes the input power conversion function and provides basic power supply for other modules of the onboard computer. The power module 4 is divided into three parts: one part supplies power to the processor module 1, and the control module can control the power on and off according to the scenario requirements to realize fault handling of the processor module 1; another part supplies power to the control module 2; and the third part supplies power to the storage module 3, and can control the power on and off according to the requirements to realize memory access switching.
[0010] Among them, the external interface module 5 realizes the external information interaction of the spaceborne computer device. The information types are mainly divided into four types: low-speed service information, high-speed service information, control information, and single-board power supply interface. The low-speed service information is implemented by Phytium processor D2000V, and the interface types mainly include SPI, CAN, GPIO, UART, etc. The high-speed service information is implemented by Phytium processor D2000V, and the interface types mainly include PCIe interface, 10 Gigabit Ethernet interface, etc. The control information realizes the information interaction between the external and control modules and completes the remote control and telemetry information processing. The power supply interface provides the power supply interface for this device.
[0011] Compared with the prior art, the advantages of the present invention are as follows:
[0012] 1. This invention uses the high-performance Phytium D2000V processor, which solves the problem of insufficient computing performance of spaceborne computers.
[0013] 2. The memory of this invention adopts a multiple backup method to achieve physical triple redundancy, which can effectively prevent CPU processor startup failure caused by single-event upset. The processor runs using two-channel DDR, and each channel DDR has ECC function and is designed with error correction function to provide reliability for processor computing and operation.
[0014] 3. This invention has strong spatial adaptability and adopts two software refactoring measures to effectively solve abnormal problems during processor refactoring.
[0015] 4. The present invention has a simple structure, high integration, and rich external interfaces, and can be adapted to a variety of satellite processing payloads, with good adaptability. Attached Figure Description
[0016] Figure 1This is a block diagram illustrating the electrical principle of the present invention.
[0017] Figure 2 This is a detailed diagram of the processor module of the present invention.
[0018] Figure 3 This is a detailed functional composition diagram of the control module of the present invention.
[0019] Figure 4 This is a detailed diagram of the storage module of the present invention. Detailed Implementation
[0020] The following is combined Figure 1 , Figure 2 , Figure 3 , Figure 4 The present invention will be described in detail below.
[0021] like Figure 1 As shown, a spaceborne computer device based on a D2000V processor includes the following components: processor module 1, control module 2, storage module 3, power supply module 4, and external interface module 5.
[0022] like Figure 2 As shown in the diagram, the processor module 1 of this invention comprises a Phytium D2000V processor, DDR4 memory, a clock, an external debugging network port, and a serial port, forming the minimum hardware system for CPU operation. The processor chosen is the Phytium D2000V, which integrates eight 64-bit cores with a clock speed of 1.6GHz, providing high processing performance. The processor module 1 is equipped with dual-channel DDR4 memory, allowing independent operation of each channel to prevent complete processor failure due to a single-channel DDR malfunction. The total memory capacity is ≥8GB and can be expanded to 16GB. The memory features ECC functionality for error correction and detection during program execution. The processor module 1 outputs multiple interfaces, including a low-speed information processing interface, a high-speed information interface, and a clock interface, enabling information exchange with external systems via the external interface module 5. The processor module 1 internally includes an ADC acquisition function to monitor processor voltage, temperature, and power consumption changes in real time.
[0023] like Figure 3As shown in the diagram, the control module 2 of this invention is implemented using an antifuse or Flash FPGA, featuring high reliability and radiation resistance. The control module 2 primarily performs remote control and telemetry information processing, program refactoring management, storage channel selection, CPU startup control, CPU on-orbit operation status monitoring, fault diagnosis, and power management. Depending on specific requirements, the control module 2 controls the processor's startup and power supply, parses input remote control commands, controls the processor's power-on and power-off, performs automatic startup upon processor power-on, or monitors abnormal processor states to achieve autonomous power-on / off control. Based on collected data, such as hardware status and processor operating status, the control module 2 determines the processor's operating status and power supply status, assesses whether a single-event fault has occurred or whether the processor temperature is too high, handles processor malfunctions in real time, improves adaptability to the space environment, and transmits relevant telemetry information to the ground through telemetry information processing, achieving on-orbit status log storage. Depending on the scenario requirements, different memory locations are selected as the startup program.
[0024] The processor operates in different working modes. During processor startup, the FPGA acts as a pass-through gate, performing no processing on the processor startup instructions or error correction / detection on memory output data, thus avoiding abnormal issues during startup. The program refactoring management function in control module 2 includes two forms: FPGA refactoring and processor refactoring. It can switch between FPGA refactoring and processor refactoring based on remote control commands. When using FPGA refactoring, the refactored data does not need to pass through the processor; the FPGA caches the data and directly performs read, write, and verification functions on the memory. This refactoring method is highly reliable and can be used in case of processor startup failure. When using processor refactoring, the FPGA acts as a pass-through channel, not processing the refactored data or instructions. The processor directly reads, writes, and verifies data on the memory through the FPGA, achieving on-orbit refactoring of the memory's stored content. This refactoring method features large refactored data capacity and fast refactoring speed. During on-orbit operation, processor refactoring is preferred for rapid refactoring of large-capacity software, while FPGA refactoring serves as a backup solution.
[0025] like Figure 4As shown in the detailed composition diagram of the storage module of the present invention, storage module 3 implements the processor's program storage function and adopts a multi-redundant physical backup form. Firstly, it achieves multiple program backups during on-orbit operation; secondly, it designs multiple memory chips to achieve tri-modal redundancy, enhancing the processor's adaptability to the spatial environment during startup. This effectively avoids processor startup failures caused by single-event upsets of memory chips, improving the high reliability of the startup program. The program storage is divided into four groups: fixed location memory 1, loaded location memory 1, fixed location memory 2, and loaded location memory 2. Memory 1 stores the processor boot file, and memory 2 stores the processor system and application files. The memory type adopts SPI interface, and the four memory groups use four SPI buses to avoid overall memory access failure caused by bus failures. Fixed location memory 1 and loaded location memory 1 each select one small-capacity radiation-resistant SPI-type Nor Flash memory, such as JFM25FL032RH, as the processor's boot file memory, storing the processor's minimum operating system. This location memory has radiation-resistant characteristics, meeting the high reliability startup requirements. Both the fixed-location memory 2 and the top-location memory 2 select three large-capacity COTS-type SPI NorFlash memories as the system and application software memory for the processor. Each group uses three memories to achieve tri-modal redundancy, effectively avoiding processor startup problems caused by single-event upsets. Furthermore, after the processor completes boot, the control module 2 selects different memory groups according to remote control commands. The processor sequentially reads the contents of the three memories in that group, achieving tri-modal redundancy and ensuring safe startup of the processor system and application programs, achieving low cost and high reliability. In addition, the fixed-location memory and the top-location memory are powered by different power supply devices, allowing for power-on and power-off control as needed. During processor operation, power is cut off to idle memories, effectively preventing single-event events caused by space radiation and improving design reliability.
[0026] The power module 4 converts the input power and provides basic power to other modules of the onboard computer. The power module 4 is divided into three parts: one part supplies power to the processor module 1, and the control module 2 can control the power on and off according to the scenario requirements to handle the faults of the processor module 1; another part supplies power to the control module 2; and the third part supplies power to the storage module 3. The power module 3 can control the power on and off according to the requirements to achieve memory access switching.
[0027] The external interface module 5 enables the onboard computer to interact with external systems. The information types are mainly divided into four categories: low-speed service information, high-speed service information, control information, and single-board power supply interface. Low-speed service information is implemented using a Phytium D2000V processor, with interface types including SPI, CAN, GPIO, and UART. High-speed service information is also implemented using a Phytium D2000V processor, with interface types including PCIe and 10 Gigabit Ethernet. The control information module facilitates information exchange between the external system and the control module, processing remote control, telemetry, and reconfiguration information. The power supply interface provides the power for this device, with an input voltage range of 5V to 12V. The connectors use FMC high-density, high-speed connectors to achieve high-speed signal transmission.
[0028] This invention features high performance, low cost, and high reliability. The device comprises five parts: a processor module, a control module, a storage module, a power supply module, and an external interface module. It is simple in composition, modular in function, and offers a rich array of external interfaces with strong adaptability. The device utilizes the high-performance Phytium D2000V processor, significantly improving the processing performance of the onboard computer and meeting the computing performance requirements of various application scenarios, including communication, computing, storage, and networking. It employs antifuse-type or Flash-type FPGAs to implement control and management functions, enabling health management of the processor and ensuring high on-orbit reliability, effectively preventing operational failures caused by single-event events. The storage module consists of radiation-hardened memory and COTS-type memory. The COTS-type devices use physical backup to achieve multiple backups of the processor program, implementing triple-modular redundancy to prevent single-event upsets from causing CPU startup problems, thus effectively reducing costs while meeting space reliability requirements.
Claims
1. A spaceborne computer device based on a D2000V processor, characterized in that, It includes a processor module (1), a control module (2), a storage module (3), a power supply module (4), and an external interface module (5). The processor module (1) includes a processor, DDR4 memory, a clock, an external debugging network port, and an external debugging serial port, forming the minimum hardware system for the processor CPU to run; The control module (2) realizes remote telemetry information processing, program refactoring management, storage channel selection, CPU startup control, CPU on-orbit operation status management, and fault diagnosis and health management functions. The storage module (3) implements the processor's program storage function. The program storage is divided into boot memory, system and application memory. The memory type adopts SPI interface form Nor Flash memory and adopts multiple redundancy physical backup form. The power module (4) realizes the conversion of input power and provides basic power supply functions for other modules of the onboard computer. The power module (4) is divided into three parts: one part supplies power to the processor module (1), and the control module (2) controls the power on and off according to the scenario requirements to realize the fault handling of the processor module (1); another part supplies power to the control module (2); and the third part supplies power to the storage module (3) and controls the power on and off according to the requirements to realize the memory access switching. The external interface module (5) enables the external information interaction of the onboard computer device.
2. The spaceborne computer device based on the D2000V processor according to claim 1, characterized in that, The processor in the processor module (1) is a Phytium D2000V processor, and the memory is equipped with two-channel DDR4 with ECC error correction and detection function.
3. The spaceborne computer device based on the D2000V processor according to claim 1, characterized in that, The control module (2) implements program refactoring management function and adopts two methods to realize on-orbit software refactoring: one is to use FPGA to realize refactoring and the other is to use processor to realize refactoring. The two refactoring methods can be switched by remote control command according to the needs. It has CPU on-orbit health management function, which monitors the processor's running status in real time. The hardware status includes voltage, power consumption and temperature, and realizes real-time fault handling of processor operation.
4. A spaceborne computer device based on a D2000V processor according to claim 1, characterized in that, The storage module (3) adopts a multi-redundant physical backup form to realize the program storage function, enhance the adaptability of the processor space environment. The storage module (3) includes a solid location memory and an up-fill location memory, which are implemented by using radiation-resistant memory or COTS type memory. The radiation-resistant memory stores the processor's running boot file, and the COTS type memory stores the processor's system and application software. The COTS type memory uses multiple memory chips to realize triple redundancy. The solid location memory and the up-fill location memory are powered by different power supply devices, and the power-on and power-off control is performed according to the requirements.