178 results about "RC circuit" patented technology

The invention relates to an RC circuit health state assessment method, belongs to the technical field of circuit health management of equipment, and solves the technical problems of circuit health state assessment inaccuracy and high calculation cost caused by an algebraic ring in the prior art. The method comprises the following steps: constructing a multi-physics field coupling degradation model and a block diagram simulation model of the RC circuit device; the simulation module is used for acquiring a block diagram simulation model; converting the simulation module into a directed graph and obtaining an algebraic ring candidate set; determining a solving execution sequence of the simulation modules; establishing an algebraic ring solver according to a trust region broken line method; and obtaining a complete dynamic response result of the RC circuit device multi-physical field coupling degradation model in the whole simulation time by using an algebraic ring solver, and evaluating the health state of the RC circuit. According to the method, the algebraic ring in the degradation model can be accurately identified and efficiently processed, so that the physical authenticity of a degradation mechanism is ensured, and high-precision tracking of RC circuit performance and reliable evaluation of health state indexes are realized.

The invention discloses a composite voltage generation device and a cable insulation performance evaluation system and method, and relates to the technical field of high-voltage insulation testing. The composite voltage generating device comprises a synchronous controller, a direct current source, an impact source, an IGBT active protection unit and a magnetic isolation coupler, and by means of the excellent characteristics of the IGBT and the magnetic isolation coupler, the superposition time sequence accuracy of direct current and impact voltage is improved, and waveform distortion is reduced. The IGBT active protection unit comprises a first IGBT and a second IGBT, and direct-current voltage polarity switching can be realized through selective conduction of the IGBTs; the RC circuit is connected in parallel between the collector electrode of the first IGBT and the emitter electrode of the second IGBT, reverse current flowing back to the direct current source direction can be discharged through the RC circuit, the risk of energy flowing back is reduced, meanwhile, the magnetic isolation coupler can completely block direct current, and an impact source is protected against the influence of direct current voltage; according to the invention, the authenticity and reliability of cable insulation performance evaluation can be effectively improved.

The invention discloses a resistance-capacitance circuit constant current precision control method, and relates to the technical field of resistance-capacitance circuits, and the method specifically comprises the steps: S1, constructing a resistance-capacitance circuit topology, and building a small signal model based on the resistance-capacitance circuit topology; s2, double-closed-loop control of an outer current loop and an inner voltage loop is adopted, a reference voltage signal is generated in the outer current loop through a PI controller, and current tracking is achieved in the inner voltage loop based on a nonlinear algorithm; and S3, introducing a dynamic compensation mechanism, and adaptively inhibiting a precision error through feed-forward compensation and parameters. According to the invention, double closed-loop control of outer loop current and inner loop voltage is adopted, and dynamic compensation is carried out on current errors through feed-forward compensation and parameter self-adaption. And the constant current precision control of the multi-branch resistance-capacitance circuit is realized by precisely calculating the duty ratio and performing closed-loop correction.

The present disclosure discloses an electrical discharge circuit. A voltage-dividing circuit performs voltage division on a voltage input terminal. A detection circuit generates a boosted detection signal. A first inverter is coupled to a first voltage feeding terminal and a second inverter input terminal. A second inverter is coupled to a first inverter output terminal and a ground terminal. A capacitor circuit of a RC circuit is coupled to the first voltage feeding terminal through a resistor to be charged to provide electric charges to the inverter input terminals. A first switch circuit is coupled to one of the inverter input terminals and the ground terminal. The boosted detection signal turns on and off the first and the second switch circuits respectively when an ESD input occurs such that a first and a second discharge transistors controlled by the inverter output terminals turn on to discharge the voltage input terminal.

The invention discloses a universal detection system and method for providing different types of connection interfaces, and the method comprises the steps: simulating a boundary scanning element through an FPGA chip of a universal test card, and cooperating with an RC circuit and a differential signal mode conversion element; therefore, different types of to-be-tested interfaces can be provided, the same general test card can be used for pin detection of an input and output pin, a grounding pin, a differential signal pin, a power supply pin and a differential clock signal pin, and the technical effect of universal detection of different types of connection interfaces can be achieved.

The utility model discloses a power supply module and an SoC chip, and belongs to the field of circuits. The power supply module provided by the utility model comprises a voltage stabilizing diode, a first RC circuit and a first power supply chip, the first power supply chip is provided with an input pin, an enabling pin and an output pin; an input pin of the first power supply chip is connected with the power supply end, an enabling pin of the first power supply chip is connected with the power supply end through the first RC circuit and the voltage stabilizing diode in sequence, and an output pin of the first power supply chip is coupled with the first voltage output end; wherein the positive electrode of the voltage stabilizing diode is connected with the first RC circuit, and the negative electrode of the voltage stabilizing diode is connected with the power supply end.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

The invention discloses a lithium battery system state-of-charge estimation method based on a Hammerstein model, and the method comprises the steps: constructing a second-order RC circuit equation of a lithium battery, describing a dynamic linear module of the Hammerstein model through a noise transfer function model, and constructing a lithium battery system through a static nonlinear module of an adaptive neural fuzzy network; designing a Gaussian signal, inputting the Gaussian signal into the agent model of the lithium battery system to obtain corresponding Gaussian signal output, and decoupling the static nonlinear module and the dynamic linear block by using the covariance function characteristic of the Gaussian signal; identifying parameters of the noise transfer function model by using a least square method based on a covariance function, solving parameters of the adaptive neural fuzzy network by using a crown porcupine optimization algorithm, and updating the weight of the adaptive neural fuzzy network by using a stochastic gradient algorithm with a forgetting factor; and constructing an OCV-SOC curve of the open-circuit voltage and the state of charge by adopting polynomial fitting, and taking output obtained by the Hammerstein model as input of the polynomial fitting to obtain an estimated value of the state of charge SOC.

An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

And a power supply circuit for generating a non-thermal plasma, optionally for a therapeutic plasma. The non-thermal plasma is generated remotely by a conduit-like device that is flexible, narrow (e.g., diameter lt; 5 mm), and extends along the longitudinal direction, and can extend into the body cavity by 50-100 cm. The plasma probe power transfer cable is part of the power supply generation circuit, whose intrinsic impedance contributes to and limits the time constant of a synchronous RC circuit whose resonant frequency is synchronized with the frequency of power generation by feedback. Variable length, structure, and / or fabrication of the plasma probe, for example, may result in different time constants. In some embodiments, the transformer coupling is divided into multiple stages, allowing the inductance of the last stage transformer to be selected with sufficient margin to mask the variability of the probe and maintain a target operating frequency using a compensation component. Various selections and / or configurations for providing compensation components are disclosed herein.

The invention relates to the technical field of power electronics, and discloses an alternating-current static switch topology with a buffering function and a design method of the alternating-current static switch topology. The alternating-current static switch topology comprises a bridge circuit and a buffer circuit, the buffer circuit comprises a first resistor, a first capacitor and a piezoresistor, the first resistor and the first capacitor are connected in series and then connected to the two ends of the bridge circuit in parallel, and the piezoresistor is connected to the two ends of the bridge circuit in parallel. According to the alternating-current static switch topology, the IGBT transistors of the bridge circuit achieve circuit mu s-level rapid opening and closing switching, and opening and closing rapidity is guaranteed; when the IGBT transistor of the bridge circuit is switched off, the piezoresistor of the buffer circuit and the RC circuit absorb the peak voltage of the IGBT transistor when the large current is switched off, so that the IGBT transistor is prevented from generating relatively high voltage stress due to system inductive reactance, the safe and stable work of the IGBT transistor in the bridge circuit is ensured, and the reliability and the stability of the application of the alternating current static switch are improved.

The invention discloses an intelligent pipeline detection and maintenance method and system based on multi-source new energy supply, and the method comprises the following steps: collecting energy through a photovoltaic power generation module, a fluid energy recovery module and a temperature difference thermoelectric conversion module, and inputting the collected energy into an energy storage device; the intelligent energy management system monitors the power generation states of the photovoltaic power generation module, the fluid energy recovery module and the temperature difference thermoelectric conversion module in real time through sensor data of each module and a deep learning model, and predicts the power generation trend of each module; the charging states of the photovoltaic power generation module, the fluid energy recovery module and the temperature difference thermoelectric conversion module are monitored based on a first-order RC circuit model, and the charging states are predicted by using a Kalman filtering algorithm; according to maintenance tasks executed by the multi-degree-of-freedom mechanical arm, charging sorting is conducted on the multiple tasks based on a data fusion algorithm, and it is ensured that the multi-degree-of-freedom mechanical arm always has enough energy support in the task execution process.

A semiconductor storage device includes a memory cell array and a peripheral circuit disposed at least partially below the memory cell array. The peripheral circuit includes an RC circuit in which a resistive portion and a capacitive portion are electrically connected to each other in series. The resistive portion includes first and second lower conductors at a level that is below the memory cell array, an upper conductor at a level that is above the memory cell array, a first contact that connects the first lower conductor to the upper conductor, and a second contact that connects the upper conductor to the second lower conductor. The first lower conductor, the first contact, the upper conductor, the second contact, and the second lower conductor are electrically connected in series in this order and the first lower conductor is closest to the capacitive portion.

Circuit structure comprising: a resistor-capacitor circuit (RC circuit) (110) having a first node (A), a second node (B) separated from the first node (A) by a resistive element (112) and a capacitive element (114), and a third node (C) between the resistive element (112) and the capacitive element (114); a trigger transistor (122) having a pair of source / drain (S / D) terminals connected between the first node (A) and the second node (B) in parallel with the RC circuit (110) and a gate terminal coupled to the third node (C) of the RC circuit (110); a mirror transistor (126) having a pair of S / D terminals coupled between the first node (A) and the second node (B) in parallel with the RC circuit (110), and a gate terminal coupled to the gate terminal of the trigger transistor (122), wherein a current through the pair of S / D terminals of the mirror transistor (126) is smaller than a current through the pair of S / D terminals of the trigger transistor (122); and a snapback device (130) having a gate terminal (T Gate ) for controlling the current flow in the snapback device (130), the snapback device (130) comprising: a P-well (142) having a first N-doped region (146) coupled to one of the first nodes (A), an N-well (144) adjacent to the P-well (142) and having a first P-doped region (148) coupled to the second node (B), wherein a current path from the first node (A) to the second node (B) runs through the snapback device (130) in parallel with the RC circuit (110), and at least one doped region within the P-well (142) or the N-well (144) coupled to a selected one of the pair of S / D terminals of the mirror transistor (126) and the gate terminal (T Gate ) of the snapback device (130), wherein the at least one doped region has a same doping type with respect to the P-well (142) or the N-well (144).

The present disclosure relates to a battery cell balancing apparatus and method, and a battery management system, and provides a battery cell balancing apparatus and method for balancing a battery cell even when an abnormality has occurred in an internal circuit of a battery management system (BMS). A mechanism can also extend the service life of the battery pack by allowing a balancing function to be used to the maximum within a range in which cell voltage measurement errors can be compensated. To this end, the present disclosure provides a configuration to determine whether an abnormality has occurred in an RC circuit of a BMS based on a cell voltage of a battery cell measured by the RC circuit, and to control a switching time of a balance switch to compensate for a cell voltage measurement error caused by the abnormality in the RC circuit.

The invention relates to the technical field of power electronics, and discloses an alkaline electrolytic cell shutdown discharge circuit which comprises a voltage sampling module, a logic control module, a solid-state switch driving module, a bleeder resistor module and a protection module. The voltage sampling module monitors direct-current high voltage of the electrolytic cell in real time and generates low-voltage signals. The logic control module receives the low-voltage signal, compares preset upper and lower threshold voltages, and generates a control signal or a stop signal. And the solid-state switch driving module amplifies the control signal and drives the power switch device to be switched on. The bleeder resistor module converts electric energy into heat energy for dissipation through a power switch device and a bleeder resistor. The protection module absorbs turn-off surges through a fast recovery diode or an RC circuit to protect the power switch device. The system adopts an all-solid-state device to replace a mechanical relay, avoids arc generation, realizes rapid and controllable discharge through closed-loop control, prolongs the service life of equipment, and is suitable for shutdown discharge requirements of the alkaline electrolytic cell in an industrial environment.

To provide an ESD protection circuit which is not operated when a normal power supply is started and even when a power supply voltage is modulated at a normal operation.SOLUTION: An RC circuit 110 is connected serially between a VDD and a GND. An RC circuit 120 is connected serially between the VDD and the GND, and a time constant that is different from the time constant of the RC circuit 110 is set. In an inverter circuit 210, a potential between a resistance element 111 and a capacitance element 112 is set to an input. In an inverter circuit 220, a potential between a resistance element 121 and a capacitance element 122 is set to an input. In an NMOS transistor 310, an output of the inverter circuit 210 is input into a gate terminal, and a drain terminal is connected to the VDD. In an NMOS transistor 320, an output of the inverter circuit 220 is input into the gate terminal; the drain terminal is connected to a source terminal of the NMOS transistor 310; and the source terminal is connected to the GND.SELECTED DRAWING: Figure 3

A method for determining whether a touch panel is applicable to a firmware is provided. The method comprising: obtaining a first signal value of a RC circuit corresponding to a reference point on a touch panel by a touch sensitive processing apparatus using mutual capacitance sensing; deploying a test conductive object to the reference point and obtaining a second signal value of the RC circuit by the touch sensitive processing apparatus, wherein the test conductive object and the touch sensitive processing apparatus share a common reference voltage; calculating a test variance ratio according to the first and the second signal values; and determining whether the touch panel is applicable to a range of touch sensing parameters supported by a firmware of the touch sensitive processing apparatus according to the test variation value and a first reference value.

Disconnecting device (30, 30') for a battery comprising several interconnected battery cells (21, 22, 23, 24) and a first and a second power supply connection (18, 19), wherein the disconnecting device (30, 30') comprises a disconnecting element (31), in particular a pyrotechnic disconnecting element (31), with which the battery cells (21, 22, 23, 24) or a part thereof can be disconnected from at least one power supply connection (18, 19) in the event of a short circuit, and wherein the disconnecting device (30, 30') further comprises a passive current- or voltage-controlled release circuit (32) which is connected in parallel to one or more battery cells (21, 22, 23, 24), wherein the release circuit (32) is a current-controlled release circuit and the release element (321) is an RC circuit (C1, R11, R12) with a capacitor (C1) serving as a current source, which is connected in series with at least one series resistor (R11, R12),wherein the triggering circuit (32) further comprises an ignition circuit (33) connected in parallel to a triggering element, which is adapted to trigger upon a predefined voltage drop in one or more of the battery cells (21, 22, 23, 24) and to close the current path to the pyrotechnic isolating element (31), and the ignition circuit (33) comprises at least a fuse resistor (R2) and a thyristor (T1), characterized in that the triggering circuit (32) is a current-controlled triggering circuit and the fuse resistor (R2) is smaller than a series resistor (R11, R12).

The invention provides a down-sampling repetitive controller applied to a three-phase four-leg inverter, and the controller comprises an ADC sampling unit which is used for sampling an output phase voltage and an inductive current of the three-phase four-leg inverter at a switching frequency F (S), and converting the output phase voltage and the inductive current into an alpha beta 0 reference system through Clark transformation; the repetitive control unit is used for subtracting the output phase voltage and the inductive current after the Clark transformation from a reference voltage and a reference current to obtain an error voltage signal and an error current signal, applying the error voltage signal and the error current signal to an RC (Resistance-Capacitance) circuit, and performing down-sampling according to a preset proportion; and performing state feedback control on the output of the RC circuit so as to generate a three-dimensional space vector modulation component to act on the three-phase four-leg inverter. The method has the advantages that (1) a closed-loop system pole is arranged by using a state feedback strategy to stabilize the system, so that LPF does not need to be introduced; and (2) designing an integer phase lead compensator.

The present disclosure discloses an electrical discharge circuit. A voltage-dividing circuit performs voltage division on a voltage input terminal. A detection circuit generates a boosted detection signal. A first inverter is coupled to a first voltage feeding terminal and a second inverter input terminal. A second inverter is coupled to a first inverter output terminal and a ground terminal. A capacitor circuit of a RC circuit is coupled to the first voltage feeding terminal through a resistor to be charged to provide electric charges to the inverter input terminals. A first switch circuit is coupled to one of the inverter input terminals and the ground terminal. The boosted detection signal turns on and off the first and the second switch circuits respectively when an ESD input occurs such that a first and a second discharge transistors controlled by the inverter output terminals turn on to discharge the voltage input terminal.

The invention discloses a gate oxide layer protection circuit, a chip and electronic equipment, and belongs to the technical field of electronic circuits. Two trigger signals are sent out in response to the voltage of a power rail through a series RC (Resistance-Capacitance) circuit; the series RC circuit responds to the condition that the voltage of the power rail is larger than a preset value, sends a connection trigger signal from a first node to connect the switching circuit, responds to the condition that the voltage of the power rail is smaller than the preset value and peak voltage appears, and sends a disconnection trigger signal from the first node based on the coupling effect of the first capacitor to cause the switching circuit to be disconnected. The first node is a common contact of the first resistor and the first capacitor; the functional circuit is connected with the first power rail, comprises a field effect transistor and is used for executing corresponding functions; the switching circuit responds to the connection trigger signal to connect the grid electrode of the field effect transistor and the second power rail, and responds to the disconnection trigger signal to disconnect the connection between the grid electrode of the field effect transistor and the second power rail; therefore, the reliability of the chip is improved.

The invention provides an automatic work recording system and method for electronic equipment for an aircraft, and belongs to the technical field of measurement and control communication, and the system is characterized in that an RC circuit outputs discharge to provide a working voltage for a detection CPU minimum system circuit after the power supply voltage of to-be-detected equipment is closed; the voltage conversion circuit converts the power supply voltage of the to-be-detected device into the input voltage which can be monitored by the detection CPU minimum system circuit and then generates a voltage conversion result. And the CPU minimum system detection circuit monitors the voltage of the to-be-detected equipment according to the voltage conversion result, records the power-on duration when the voltage is greater than a preset threshold value, and stores the power-on duration into the storage circuit within the delay time of the RC delay circuit when the voltage is not greater than the preset threshold value. According to the voltage conversion result, the work of the to-be-tested equipment is automatically recorded, and the working time of the to-be-tested equipment is more accurately recorded, so that the electronic equipment is fully utilized, and the use and maintenance cost of the aircraft is reduced.

The present invention provides a clock signal generator and a frequency trimming method that can trim the clock frequency with high resolution. [Solution] The clock signal generator includes an oscillator circuit and a charge transfer capacitor. The oscillator circuit is configured to generate a clock signal and includes a comparator and a resistor-capacitor (RC) circuit, the RC circuit including a capacitor. The charge transfer capacitor is connected to the RC circuit. The frequency of the clock signal is trimmed by injecting or extracting charge associated with the RC circuit through the charge transfer capacitor.

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

A power supply system of an intelligent processing chip belongs to the technical field of space power supplies. The slow start circuit controls voltage between a source electrode and a grid electrode of an FET tube through a RC circuit of the slow start circuit to achieve the purpose of slow start, and input charging surge current generated at the moment of power-up is reduced; the input filter circuit is used for allowing low-frequency pulse current to flow through and suppressing high-frequency noise interference; the power supply module is used for carrying out DC-DC conversion on the voltage signal; the output filter circuit is used for allowing low-frequency pulse current to flow through and suppressing high-frequency noise interference; the power supply modules and the output filter circuits are in one-to-one correspondence to form multi-path output; the FPGA control and feedback circuit is used for dynamically adjusting interval time of different paths of output voltage according to requirements and carrying out feedback control on amplitudes of the different paths of output voltage; and monitoring the temperature of each group of power supply modules in real time, and performing feedback control on the output power of the power supply modules.

This invention discloses a lightning strike sensor to address the problem of successfully acquiring lightning parameters and implementing the sensor in practical application environments when studying lightning strike parameters. The lightning strike sensor includes a 1.2 / 50μs lightning current amplitude sampling circuit and a time-width sampling circuit constructed based on a general comparator circuit and an RC circuit, connected to the lightning current amplitude sampling circuit. The time-width sampling circuit sequentially includes a wavefront time-width sampling circuit, a half-wave time-width sampling circuit, and a full-wave time-width sampling circuit. Specifically, the lightning current amplitude sampling circuit outputs the amplitude sampling level of the lightning strike waveform; the wavefront time-width sampling circuit acquires the wavefront time of the lightning strike waveform; the half-wave time-width sampling circuit acquires the half-wave time of the lightning strike waveform; and the full-wave time-width sampling circuit acquires the full-wave time of the lightning strike waveform. This allows for successful acquisition of lightning parameters and implementation in practical application environments.

The invention discloses a hardware MPPT (Maximum Power Point Tracking) control device and method for a space power supply, and belongs to the technical field of space power supplies. The hardware MPPT control device comprises a Buck circuit topology and an MTTP control circuit; the MTTP control circuit comprises a peak pickup circuit which picks up the maximum point of the power of the solar cell through charging and discharging of an RC circuit; the MPPT reference circuit is used for keeping the maximum power point of the solar cell and generating a reference signal Vmpp of MPPT; the MPPT modulation circuit is used for modulating Vsa to work on the maximum power of the solar cell by changing the duty ratio of Buck by taking a Vmpp signal representing the maximum power of the solar cell as a reference; the mirror current source sampling circuit is used for copying high-end current output by the solar cell array; and the pulse modulation multiplier realizes the product of the voltage and the current of the solar cell by using an MPPT modulation circuit and a mirror current source sampling circuit.

This utility model relates to the field of general circuit technology, specifically to a stable and anti-interference fast power-on / off RC reset circuit; it includes an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, M5, and I1, where I1 is a logic gate OR gate. The RC reset circuit of this design adds a MOSFET interlock structure to the traditional circuit architecture to generate high and low levels, which are then used by logic gate circuits to generate high and low voltage signals, suppressing reset signal jitter that may be caused by power supply noise or environmental interference. At the same time, the RC reset circuit uses a MOS resistor instead of a traditional resistor and utilizes its own substrate diode as a capacitor discharge diode, which can accelerate the discharge of capacitor C. Furthermore, a resistor discharge branch connected in parallel with capacitor C is added to achieve fast reset of the RC circuit when the power supply is rapidly powered on or off.

The application provides a bus fast-charging station orderly charging method considering battery dynamic charging loss, comprising: determining the power demand meeting bus line operation according to the operation time of the charging station, equipment power limit, quantity limit and bus departure plan; establishing a battery heat loss model and the relationship between charging energy conversion efficiency and the actual charging power of the vehicle-mounted energy storage system based on a first-order RC circuit model; taking the minimum actual power consumption of the charging station in a day or the minimum actual electricity cost of the charging station in a day as an objective function, wherein the battery heat loss is considered, and an optimization model is established with the charging station operation time, charging pile number, charging pile maximum power, power distribution capacity, electric bus travel power demand, electric bus charging time continuity as constraint conditions; using piecewise linearization to convert the nonlinear optimization objective function model into a mixed integer convex programming problem, and solving the mixed integer convex programming problem to obtain the optimal charging plan, including the optimal charging time and corresponding charging power of each vehicle. The method improves the charging energy conversion efficiency, reduces the battery heat loss and prolongs the service life of the battery, reduces the charging cost of the bus while improving the charging energy conversion efficiency, and improves the economy.