712results about "Logic circuits coupling/interface using field-effect transistors" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

The invention discloses a high-speed serial signal linear equalization circuit which comprises an input terminal, a continuous time linear equalizer (CTLE), a super source follower, a variable gain amplifier (VGA) and an adaptive feedback. The input end is connected with a 100-ohm internal resistance differential signal source of the transmitting end through a channel; the equalization circuit CTLE is connected to the output end of the input end connection module, two groups of resistance switches (RsMF and RsHF) of the CTLE module are respectively controlled by 4-bit binary codes to enable source degeneration resistors Rs of two stages of CTLEs to be variable, two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable, and the two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable. The change of a zero pole of the circuit is realized through the change of the source degeneration resistor Rs and the source degeneration capacitor Cs, and the adjustability of the difference between the high-frequency gain and the low-frequency gain of the circuit is realized, so that the multi-gear adjustability of the equalization capability is realized.

In one embodiment, a method includes: receiving, in a level shifter, an input signal from a first voltage domain that operates according to a first supply voltage; level shifting the input signal to at least one level-shifted signal having a second voltage greater than the first supply voltage; based on the at least one level-shifted signal, generating a first pulse signal and a second pulse signal; latching the first pulse signal through a latch circuit to form an output signal; and outputting the output signal to a second voltage domain, the second voltage domain to operate according to a second supply voltage greater than the first supply voltage.

The invention provides a level shifter and a memory device including the same. The level shifter includes: a medium voltage output circuit configured to output a medium voltage based on an input voltage stepped between a first voltage level and a second voltage level; a feedback circuit configured to output a feedback voltage and an output voltage stepped between a positive target voltage level and a negative target voltage level based on the positive target voltage, the negative target voltage, and the medium voltage; a pull-up voltage control circuit configured to output the first voltage or the positive target voltage to the medium voltage output circuit based on the feedback voltage; and a pull-down voltage control circuit configured to output the second voltage or the negative target voltage to the medium voltage output circuit based on the feedback voltage.

A voltage mode driver circuit has a first driver slice has a pullup structure that includes a first transistor and a second transistor and a pulldown structure that includes a third transistor and a fourth transistor. The first transistor has a gate that receives a first version of a first data signal. The second transistor has a gate that receives a first version of a second data signal. The third transistor has a gate that receives a second, complementary version of the first data signal. The fourth transistor has a gate that receives a second, complementary version of the second data signal. The first data signal encodes data in a first mode and enables the pullup and pulldown structures in a second mode of operation. The second data signal encodes data in the second mode of operation and enables the pullup and pulldown structures in the first mode of operation.

A level-shiftless transmitter includes a transmitter driver circuit. The transmitter driver circuit includes a first PMOS device, a second PMOS device, a first NMOS device, a second NMOS device, and a sub-circuit. The sources of the first and second PMOS devices are electrically coupled with each other. The gates of the first PMOS and the first NMOS devices are electrically coupled with each other. The gates of the second PMOS and the second NMOS devices are electrically coupled with each other. The sub-circuit is electrically coupled with a voltage domain to provide a voltage lower than the voltage domain to the sources of the first and second PMOS devices.

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

The present invention discloses a level conversion circuit and chip for converting an input signal in a first voltage domain into an output signal in a second voltage domain. The level conversion circuit includes: a switch unit including a first MOS transistor and a second MOS transistor, wherein the control end of the first MOS transistor and the control end of the second MOS transistor are both connected to a bias voltage; an input unit operating in the first voltage domain and connected to the second end of the first MOS transistor and the second end of the second MOS transistor; a conversion unit operating in the second voltage domain and connected to the first end of the first MOS transistor and the first end of the second MOS transistor; an output unit operating in the second voltage domain; and a clamping unit connected between the switch unit and a first low voltage. In a first state, the first high voltage is not powered off and the clamping unit is disconnected. In a second state, the first high voltage is powered off and the clamping unit is turned on to clamp the driving voltage to the second low voltage. The present invention reduces chip area and avoids power consumption caused by the DC current brought by the pull-down element.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

Provided is a buffer circuit that can realize a wide dynamic range, a reduced area, and a reduced power consumption amount while maintaining low output impedance. The buffer circuit includes a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate to which an input signal is input. The current source is connected to one terminal of the first transistor. The second transistor is connected to the other terminal of the first transistor. The output terminal is connected to the one terminal or the other terminal of the first transistor. The first and second capacitors are between the current source and the gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.

The invention relates to a buffer and an integrated circuit. The buffer includes: an operational amplifier; the first end of the voltage-voltage feedback network is coupled to the positive phase / negative phase input end of the operational amplifier; the first end of the isolation resistor is coupled to the output end of the buffer; the first group of switches and the second group of switches are controlled to be closed when the first capacitive load is driven, the second group of switches are disconnected when the second capacitive load is driven, and the first group of switches are disconnected and the second group of switches are closed when the second capacitive load is driven; in the first load, the output end of the operational amplifier is coupled to the output end of the buffer through at least one switch in the first group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the buffer through at least one switch in the first group of switches. In the second load, the output end of the operational amplifier is coupled to the second end of the isolation resistor through at least one switch in the second group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the operational amplifier through at least one switch in the second group of switches.

A high-frequency circuit includes a switch circuit having terminals and configured to switch between connection and disconnection between the terminals, and a charge pump circuit configured to supply a control voltage to the switch circuit, wherein the switch circuit includes an FET having a first gate, a first drain and a first source, where the first gate is supplied with a first control voltage from the charge pump circuit, the first drain is connected to the terminal, and the first source is connected to the other terminal, and an FET having a second gate, a second drain and a second source, where the second gate is supplied with a second control voltage from the charge pump circuit, the second drain and the second source are connected to a path connecting the terminal, the FET and the terminal, and the second drain and the second source are short-circuited.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

The invention discloses a power supply control circuit and an input and output circuit system, and the circuit employs a multi-stage NMOS tube voltage reduction module to replace a diode structure scheme in the related technology. Through cooperative work of the multi-stage voltage reduction module and the multi-stage voltage boosting module, the problem of current leakage caused by too large gate-source voltage difference of a PMOS tube in a POC circuit in the related technology is solved, and output voltage is recovered to IO power supply domain voltage through the multi-stage voltage boosting module. And a pure MOS device design is adopted, and the problem of inconsistent PN junction voltage in a diode scheme does not need to be considered, so that the layout design does not need an additional isolation region, the circuit area is reduced, and the leakage current is reduced. According to the power supply control circuit, voltage step-by-step control is realized, and customized configuration can be carried out according to different voltage domain scenes. The integrated Schmitt trigger filters power supply noise, the trigger logic of the integrated Schmitt trigger is matched with the stage number of the multi-stage voltage reduction module, correct response under different voltage difference environments is achieved, and the reverse voltage of the circuit meets the design requirement.

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

The invention discloses a high-precision active isolation type 4-20 mA current loop circuit and an HART protocol transparent transmission method thereof, and relates to the technical field of industrial automation signal transmission, the high-precision active isolation type 4-20 mA current loop circuit comprises an input side, an output side and an isolation layer, the input end is connected with the transient protection circuit, the transient protection circuit is connected with the LC pi-type filter circuit, and the transient protection circuit and the LC pi-type filter circuit are respectively connected with the current reverse connection protection circuit. The influence of ground loop interference and common-mode voltage on the system is avoided, the safety of signal transmission is ensured, and the 3000Vrms withstand voltage requirement of an industrial scene is met. The interference of high-frequency noise on HART signals and 4-20mA analog signals is suppressed by optimizing the filter circuit and the EM I optimization layout.

A semiconductor integrated circuit includes a front stage circuit and a rear stage circuit. The rear stage circuit includes first, second, fifth, and sixth transistors and a plurality of seventh transistors. The front stage circuit includes first and second inverters and third and fourth transistors. The third transistor is between the first inverter and the rear stage circuit, and has a gate connected to a first power supply node. The fourth transistor is between the second inverter and the rear stage circuit, and has a gate connected to the first power supply node. A breakdown voltage of each of the third and fourth transistors in the front stage circuit is lower than that of the first, second, fifth, sixth, and seventh transistors in the rear stage circuit.

The invention provides a level conversion circuit and a level conversion method, and belongs to the technical field of semiconductor integrated circuits. The circuit comprises a conversion module and a voltage supply module, when an input signal is a low level from a previous voltage domain, the voltage supply module can reduce a second power supply voltage by a certain threshold value, so that current can be completely cut off at the joint of the conversion module and the voltage supply module, and when the input signal is a high level from the previous voltage domain, the voltage supply module can reduce the second power supply voltage by a certain threshold value. The second power supply voltage from the voltage supply module can output a voltage converted into a signal suitable for a second voltage domain. And on a high-level voltage conversion output path, the number of the MOS tubes and the distance between the adjacent MOS tubes are controlled, so that the number of the MOS tubes can be greatly reduced, the layout is saved, the resistance is reduced, and the power consumption is reduced.

Circuits and methods that enable a “break-before-make” process for an electronic switch that avoids the relatively large time delays of fixed time delay circuitry. Logic gates, rather than a time delay, are used to lock out an input switch through-path from turning ON before another input switch through-path is fully turned OFF. An embodiment includes a first and second monitor logic blocks, configured such that (1) a first through-path is turned OFF before a first shunt-path is allowed to turn ON and before a second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before a second through-path is allowed to turn ON; and (2) the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

A current-integrating summing circuit is provided, and may include a first capacitor and a second capacitor to integrate an input current over time, a first pair of transistors to receive a differential pair of input signals, a second pair of transistors to receive a common-mode voltage, a third pair of transistors and a fourth pair of transistors respectively configured in a cascode formation relative to the first pair of transistors and the second pair of transistors, and a pair of complementary clocks to activate the third pair of transistors to enable charging of the first and second capacitors according to the differential pair of input signals during an integration phase, wherein the pair of complementary clocks are to activate the fourth pair of transistors to enable discharging of the first and second capacitors during a reset phase.

Provided is a novel drive circuit. A level shift circuit has first to third transistors, first to third power supply lines, and first to fourth wiring lines. A back gate of the first transistor is electrically connected with the first wiring line. One of a source and a drain of the first transistor is electrically connected with the first power supply line. The potential of the first power supply line is higher than the potential of the second power supply line, the potential of the third power supply line is lower than the potential of the first power supply line and the potential of the second power supply line, the signal of the fourth wiring line switches from a low potential level to a high potential level when the signal supplied to the first wiring line is at a high potential level, and the signal of the fourth wiring line switches from the high potential level to the low potential level when the signal supplied to the first wiring line is at a low potential level.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A signal transmission device has an initial signal stabilization mechanism and includes a driver and a bypass circuit. The driver includes: a first current source circuit coupled between a high voltage terminal and a first node; a second current source circuit coupled between a low voltage terminal and a second node; and a driving circuit coupled between the first node and the second node. The driving circuit outputs an output signal according to a first bias voltage of the first node, a second bias voltage of the second node, and an input signal during a signal output operation. The bypass circuit is coupled between the first node and the second node. In the beginning of the signal output operation, the bypass circuit conducts a current from the first node to the second node to assist in establishing the first and second bias voltages and thereby stabilize the output signal.

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

The application discloses a kind of anti-radiation reinforcement circuits of fast radiation charge, it is related to the field of semiconductor integrated circuit design.The present application is to solve the problem of large area, large power consumption of existing circuit level anti-radiation reinforcement mode, and cannot be applied in the anti-radiation reinforcement design of analog circuit.The voltage generating circuit of the present application is used to provide voltage for charge discharge circuit to trigger charge discharge circuit, so that the charge radiated to the output node of charge discharge circuit is discharged.When the positive voltage pulse of output end appears due to the positive charge pulse generated by radiation particle, the gate of positive charge discharge tube appears positive voltage pulse, the positive charge discharge tube is turned on, and the negative charge discharge tube is closed, so that the positive charge radiated to the output end is discharged;When the negative voltage pulse of output end appears due to the negative charge pulse generated by radiation particle, the gate of negative charge discharge tube appears negative voltage pulse, the negative charge discharge tube is turned on, and the positive charge discharge tube is closed, so that the negative charge radiated to the output end is discharged.