415results about "Logic circuits coupling/interface using field-effect transistors" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

A voltage mode driver circuit has a first driver slice has a pullup structure that includes a first transistor and a second transistor and a pulldown structure that includes a third transistor and a fourth transistor. The first transistor has a gate that receives a first version of a first data signal. The second transistor has a gate that receives a first version of a second data signal. The third transistor has a gate that receives a second, complementary version of the first data signal. The fourth transistor has a gate that receives a second, complementary version of the second data signal. The first data signal encodes data in a first mode and enables the pullup and pulldown structures in a second mode of operation. The second data signal encodes data in the second mode of operation and enables the pullup and pulldown structures in the first mode of operation.

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

Provided is a buffer circuit that can realize a wide dynamic range, a reduced area, and a reduced power consumption amount while maintaining low output impedance. The buffer circuit includes a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate to which an input signal is input. The current source is connected to one terminal of the first transistor. The second transistor is connected to the other terminal of the first transistor. The output terminal is connected to the one terminal or the other terminal of the first transistor. The first and second capacitors are between the current source and the gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

Provided is a novel drive circuit. A level shift circuit has first to third transistors, first to third power supply lines, and first to fourth wiring lines. A back gate of the first transistor is electrically connected with the first wiring line. One of a source and a drain of the first transistor is electrically connected with the first power supply line. The potential of the first power supply line is higher than the potential of the second power supply line, the potential of the third power supply line is lower than the potential of the first power supply line and the potential of the second power supply line, the signal of the fourth wiring line switches from a low potential level to a high potential level when the signal supplied to the first wiring line is at a high potential level, and the signal of the fourth wiring line switches from the high potential level to the low potential level when the signal supplied to the first wiring line is at a low potential level.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A signal transmission device has an initial signal stabilization mechanism and includes a driver and a bypass circuit. The driver includes: a first current source circuit coupled between a high voltage terminal and a first node; a second current source circuit coupled between a low voltage terminal and a second node; and a driving circuit coupled between the first node and the second node. The driving circuit outputs an output signal according to a first bias voltage of the first node, a second bias voltage of the second node, and an input signal during a signal output operation. The bypass circuit is coupled between the first node and the second node. In the beginning of the signal output operation, the bypass circuit conducts a current from the first node to the second node to assist in establishing the first and second bias voltages and thereby stabilize the output signal.

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

A bi-directional level shifter is described that combines an input / output (I / O) signal and a direction control signal into a single signal, thereby reducing the number of total pins. The combination of I / O and direction is encoded by different voltage levels, and thus no information is encoded by currents. This advantageously keep power consumption low compared to conventional designs. Moreover, because a predetermined voltage encoding is used in which the bi-directional level shifter is configured to detect and respond via hardware, transitions between data flow are detected very quickly.

An integrated circuit includes a first cell region including a first set of transistors of a clock circuit, and a second cell region adjacent to the first cell region along a first boundary. The second cell region includes a feed-through via extending from a front-side to a back-side of a substrate, and being configured to electrically couple elements on the front-side and the back-side together. The feed-through via includes a first conductor on the back-side of the substrate, a second conductor being on a first level and being above the first conductor, a first contact being on a second level, and being above the first conductor, and a first via being on a third level, and being above the first conductor.

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.

The present application relates to the technical field of optical coupling, and particularly relates to a constant current optical coupling isolation circuit based on a depletion mode MOSFET; through the cooperation of a reverse protection module, a self-bias constant current module and a response enhancement module, super-wide voltage input, low power consumption and high-speed dynamic response are realized in the circuit, to a certain extent, the inherent technical contradiction that the traditional resistance current limiting scheme cannot simultaneously consider reliable conduction and low power consumption under wide voltage, and the slow response of high CTR optical coupling is solved, the structure is extremely simple and the reliability is high, a self-bias constant current source based on a depletion mode MOSFET is adopted, only one resistor is needed to realize relatively accurate constant current output in a super-wide input range of 9.6V to 400V, replacing the current limiting resistor with huge power consumption under high voltage or the active constant current source with complex circuit in the traditional scheme, and the power consumption under high voltage application is reduced; the technical problem that the existing resistance current limiting scheme is limited in widening the input voltage range of the optical coupling is solved.

The application discloses a CAN transceiver circuit, which comprises a logic and timing module, a current mirror driving group and a resistance driver group; the input end of the logic and timing module is connected with a TXD signal, and the output end outputs a plurality of groups of driving signals, each group of the driving signals controls a current mirror driving group or a resistance driver group; the current mirror driving group and the resistance driver group are used for driving a CANH port and a CANL port, wherein a single CANH port or a single CANL port is provided with upper and lower current mirror driving groups and upper and lower resistance driver groups; the upper current mirror driving group is connected with the upper resistance driver group in parallel, and the lower current mirror driving group is connected with the lower resistance driver group in parallel. The application realizes the bit width consistency improvement and the adaptive baud rate through the independent impedance control of the current mirror pull structure and the differential port, and the process of adjusting the port impedance does not affect the bit width consistency.

The present disclosure relates to a level shifter for shifting a voltage signal from a first voltage domain to a second voltage domain, the level shifter comprising: an input circuit configured to receive a voltage signal in the first voltage domain, an output circuit configured to output a voltage signal in the second voltage domain, and a protection circuit configured to prevent a reverse current flow between the input circuit and the output circuit.

The application relates to a high-frequency plasma power supply, which realizes high-level response of the high-frequency plasma power supply through a voltage response board with a model of XILINX-AEC100 vehicle-level FPGA. Since the voltage applied in the high-frequency plasma power supply is higher than 400 volts, the voltage response board with the model of XILINX-AEC100 vehicle-level FPGA can realize normal work in a high-voltage environment. An isolating switch gives the voltage response board an operation action of an operator in the form of a level signal through an isolating effect, and in order to reduce the influence of voltage mutation of a voltage booster, a power selector can pre-set output electric energy power of the voltage response board. A power delay device fits large impedance between the voltage booster and a high-frequency electrotome, so as to prevent mutation of output electric power, and further improves the accuracy of the high-frequency plasma power supply in regulating electric energy supply.

Embodiments herein relate to a driver circuit for an optical modulator such as a micro-ring modulator (MRM). The driver circuit includes first and second drivers which receive respective differential data signals, and which have their output nodes coupled to a cathode and anode, respectively of the MRM. One or both of the drivers can have their output nodes alternating-current (AC)-coupled to a bias circuit which biases the voltage of the output signal to shift its voltage swing. The bias circuit can include a latch which receives Vbc_high at its power supply terminal and Vbc_low at its ground terminal, where Vbc_high>Vbc_low>0 V.

There is provided a circuit for a physical unclonable function comprising: first and second outputs; a cell comprising a plurality of CMOS devices; and a plurality of switching devices, the plurality of switching devices operable to connect a gate terminal of each of the plurality of CMOS devices to one of the first and second outputs, wherein a quantity of the plurality CMOS devices is a multiple of two, and wherein the circuit is configured such that each of the first and second output is connected to an equal quantity of the plurality of CMOS devices.

The invention discloses a pin multiplexing control circuit and a microcontroller, and the circuit comprises a voltage selection circuit which is used for outputting a first voltage according to an input voltage and a power voltage; the control end of the transmission gate is used for receiving a target control signal; the target control signal is generated based on first voltage power supply; in the first mode, the transmission gate is switched on based on a target control signal, receives an input voltage and outputs an analog voltage signal to the multiplexing pin according to the input voltage; in the second mode, the transmission gate is turned off based on the target control signal to isolate the input voltage from the multiplexing pin. The larger value of the input voltage and the power supply voltage is output through the voltage selection circuit to serve as the first voltage, and the first voltage serves as the power supply to generate the target control signal, so that in the second mode, the target control signal can provide a sufficiently high level to drive the control end of the transmission gate, reliable turn-off of the transmission gate is ensured, and the reliability of the transmission gate is improved. Therefore, the input voltage and the multiplexing pin are effectively isolated, and high-voltage signals are prevented from flowing backward.

The invention provides a high-voltage level shift circuit with high dVdt suppression capability, which is used for converting a signal in a low-voltage domain into a signal in a high-voltage domain and comprises an encyclopedia level shift module, a PMOS (P-channel Metal Oxide Semiconductor) coupling module, a noise current elimination module, a current compensation module, a transmission gate module and an RS (Reed-Solomon) latch module, the level shift module is used for transmitting signals from a low-voltage domain to a high-voltage domain, the PMOS coupling module is used for converting voltage signals transmitted by the level shift module into current signals, accelerating signal transmission and preventing common-mode signals from passing through, and the noise current elimination module is used for mirroring current, accelerating signal transmission and counteracting common-mode noise induction current. The current compensation module is used for compensating the current of a node, the transmission gate is used for transmitting a signal output by the noise elimination module to the RS latch, the RS latch module is used for recovering an edge narrow pulse signal into a square signal, and according to the scheme, the dV / dt noise suppression capability of the circuit is enhanced while low power consumption and low delay are achieved.

The invention relates to the technical field of integrated circuits, and provides a pulse trigger type level shift circuit which comprises a double-pulse current generation circuit, a high-low level shift conversion holding circuit, a high-voltage domain output shaping filter circuit and an RS trigger which are connected in sequence. The double-pulse current generating circuit responds to the jump edge of the low-voltage domain input signal to generate a transient double-pulse current signal; the high-low level shift conversion holding circuit is combined with the current signal and an input signal to generate a complementary pulse voltage signal of a high-voltage domain; the shaping and filtering circuit performs shaping and filtering on the pulse voltage; and the RS trigger finally latches the logic state and outputs a stable burr-free high-voltage domain signal. Through a pulse current triggering mode, an extremely short pulse is generated only when a signal jumps, a quiescent current path is eliminated, and low static power consumption is achieved; meanwhile, fast level flipping under high voltage difference is achieved through pulse driving, the requirement for the input signal driving capacity is low, and the characteristics of high speed and low power consumption are considered.

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

The invention relates to the technical field of PSI5 interfaces, and discloses a PSI5 interface circuit, which comprises a current-to-voltage unit, a switch unit, a threshold voltage generation unit, a comparator COMP and a logic control unit, during normal use, the current-to-voltage conversion unit, the threshold voltage generation unit, the comparator COMP and the logic control unit correctly convert sensor Manchester encoding current data conforming to a PSI5 protocol range, namely current flowing through the switch unit, into digital signals, and the digital signals are output signals of the comparator COMP; on the basis, after an open circuit or short circuit fault is removed, the output end of the comparator COMP may output a high-level signal for a long time, and at the moment, the logic control unit controls the threshold voltage output by the threshold voltage generation unit, so that the output end of the comparator COMP outputs a low-level signal; normal tracking of current and self-recovery of data are realized.

The present application relates to the field of integrated circuit technology, and provides a pulse trigger type level shift circuit, which comprises a double pulse current generating circuit, a high-low level shift conversion holding circuit, a high voltage domain output shaping filter circuit and an RS flip-flop connected in sequence. The double pulse current generating circuit generates a short double pulse current signal in response to a jump edge of a low voltage domain input signal; the high-low level shift conversion holding circuit combines the current signal with the input signal to generate a complementary pulse voltage signal in a high voltage domain; the shaping filter circuit shapes and filters the pulse voltage; and the RS flip-flop finally latches the logic state and outputs a stable high voltage domain signal without glitches. The present application generates an extremely short pulse only when the signal jumps by means of pulse current trigger, eliminates the static current path, and has low static power consumption. Meanwhile, the pulse driving is used to realize fast level inversion under high voltage difference, and the input signal driving capability requirement is low, so that the high speed and low power consumption characteristics are taken into account.

High-swing push-pull assisted Voltage Mode Logic (VML) driver circuits can enhance output voltage amplitude to improve efficiency and performance in electronic applications. For example, this is accomplished by utilizing a primary current generator circuit that is powered by a supply voltage to generate a primary current. The primary current is provided, through a switching circuit, to an output node that, in response to an input signal, generates a first output voltage. Further, a supplementary current generator circuit is coupled to the switching circuit to generate a secondary current. The combination of the primary and secondary currents increases the amplitude of the first output voltage, thereby enabling the VML driver circuit to deliver enhanced performance, particularly in applications requiring precise voltage control and high efficiency.

A semiconductor device includes a low voltage-to-high voltage level shifter. The level shifter is structured to receive a low voltage signal and output a high voltage signal. The level shifter includes a buffer structured to receive the low voltage input signal. The buffer includes a pullup transconductor, a pulldown transconductor, and a cutoff transconductor, coupled in series. The pullup transconductor has a negative transconductance and is structured to be controlled by the low voltage input signal. The pulldown transconductor has a positive transconductance and is structured to be controlled by the low voltage input signal The cutoff transconductor has a positive transconductance and is structured to be controlled by a delayed high voltage cutoff signal that inversely corresponds to the low voltage input signal.