13 results about "Gated diode" patented technology

The present disclosure relates to a binarized neural network circuitry using silicon-gated diodes. The binarized neural network circuitry according to one embodiment of the present disclosure includes a plurality of silicon-gated diodes in which a diode structure as a channel area is located between an anode terminal and a cathode terminal, a gate terminal is located on the diode structure to implement unidirectional switching through potential barrier control in the channel area based on different voltages applied to each of the anode terminal and the gate terminal, and memory characteristics are realized as holes or electrons accumulate in the potential well due to a positive feedback loop. In addition, in the binarized neural network circuitry, the silicon-gated diodes operate as synaptic elements in a memory array connected in parallel, and the results of a multiply-accumulate (MAC) operation are output based on an input signal applied from an input line processor connected to the memory array and a weight update signal applied from a synapse line processor connected to the memory array.

To provide a gate control type diode in which an allowable range of the gate pulse width is increased while an adverse influence on other main electric characteristics is suppressed.SOLUTION: A gate control type diode 110 includes a diode gate electrode embedded in a plurality of first trenches 51 in a first active region RA1 through an oxide film 6, an anode electrode embedded in a plurality of second trenches 52 in a second active region RA2 through the oxide film 6, a P-type channel layer 2 formed in a surface layer of an N-type semiconductor substrate 1 between the two adjacent first trenches 51 and between the two adjacent second trenches 52 and electrically connected to the anode electrode, and an N+ type layer 4 formed in a surface layer of the P-type channel layer 2 in the first active region RA1. The area of the first active region RA1 is 20% or more and 80% or less of the total of the area of the first active region RA1 and the area of the second active region RA2.SELECTED DRAWING: Figure 1

One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source / drain (S / D) is disposed on the substrate. The first (second) S / D has a first (second) S / D doping concentration of a first (second) S / D doping type. One or more p-n junctions form one or more respective diodes. Each of the p-n junctions has a first side and a second side. The first (second) side of the p-n junction is electrically and physically connected to the first (second) S / D and has a same type of doping, respectively. A gate stack made from a gate dielectric layer and a gate metal interfaces and surrounds each of the p-n junctions.

A self-activating binarized neural network circuit that performs the activation function by itself is provided. [Solution] The neural network circuit 400 includes a plurality of silicon gated diodes which implement unidirectional switching through potential barrier adjustment in a channel region based on different voltages applied to the anode terminal and the gate terminal, respectively, and which implement memory characteristics by accumulating holes or electrons in a potential well through a positive feedback loop, and the plurality of silicon gated diodes operate as synapse elements 401 in a memory array connected in parallel, and output a MAC operation result based on an input signal applied from an input line processing unit connected to the memory array and a weight update signal applied from a synapse line processing unit connected to the memory array.

To provide a true random number generator for realizing information encryption by generating a random bit by a stochastic switching operation through a feedback loop phenomenon in a channel region of a gate diode, and controlling a generation probability of the random bit through control of voltage application.SOLUTION: The true random number generator 300 includes a gated diode 301 and a control transistor 302. The gated diode includes a p + - i-n + diode structure disposed between a drain and a source, a gate oxide layer disposed on an intrinsic region of the p + - i-n + diode structure, and a first gate and a second gate disposed on the gate oxide layer. The control transistor includes a control drain terminal connected to the source, a control gate terminal, and a control source terminal, and controls electron injection into the p + - i-n + diode structure by controlling a gate voltage applied through the control gate terminal.SELECTED DRAWING: Figure 3A

To provide a vibration neural network circuit device for solving a graphcoloringproblem by allowing a plurality of oscillators coupled by a capacitor or a resistor to detect an edge or to indicate colors of at least two graphs for an input graph.SOLUTION: In the vibration neural network circuit device 700 using a gated diode-based oscillator, phase differences between the voltage VIN1 and the voltage VIN2 may occur due to time differences between the voltage VOUT1 and the voltage VOUT2 input to at least two gated diodes constituting at least two oscillators 701 and 702, and thus colors of at least two graphs with respect to input graphs of a graph coloring problem may be represented based on the phase differences over time.SELECTED DRAWING: Figure 7A

An electronic component includes a gate structure over a semiconductor layer. The gate structure is insulated from the semiconductor layer and includes a layer made of a magnetic material. The electronic component may form a FET transistor, a MOSFET transistor, a SET transistor, a gated diode, a gated MOS structure, or a gated quantum dot.

Disclosed is an oscillatory neural network circuitry using oscillators including a gated diode. An oscillatory neural network circuitry according to an embodiment of the present disclosure using oscillators including a gated diode can represent at least two graph colors of an input graph based on phase differences in output voltages over time, as phase differences occur in the output voltages depending on time differences of input voltages applied to at least two gated diodes constituting at least two oscillators.

The present disclosure relates to a circuit arrangement of a binarized neural network using silicon gate diodes. The circuit arrangement of a binarized neural network according to one embodiment of the present disclosure comprises a plurality of silicon gate diodes in which a diode structure is arranged as a channel region between an anode terminal and a cathode terminal, a gate terminal is arranged on the diode structure to perform unidirectional switching by means of a potential barrier control in the channel region based on different voltages applied to each of the anode terminal and the gate terminal, and storage properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop.Furthermore, in the circuit arrangement of a binarized neural network, the silicon gate diodes operate as synaptic elements in a memory arrangement connected in parallel, and the results of a multiply-accumulate (MAC) operation are output based on an input signal applied by an input line processor connected to the memory arrangement and a weight update signal applied by a synapse line processor connected to the memory arrangement.

An object is to increase a tolerance of a gate pulse width in a gate-controlled diode while suppressing detrimental effects on other main electrical characteristics. A gate-controlled diode includes: a diode gate electrode buried in each of first trenches through an oxide film in a first active region; an anode electrode buried in each of second trenches through the oxide film in a second active region; a P type channel layer formed in a surface layer of an N− type semiconductor substrate; and an N+ type layer formed in a surface layer of the P type channel layer in the first active region. An area of the first active region is 20% or higher and 80% or lower of a sum of the area of the first active region and an area of the second active region.

One object is to increase a tolerance of a gate pulse width in a gate-controlled diode while suppressing adverse effects on other main electrical properties. A gate-controlled diode 110 comprises: a diode gate electrode covered in each of first trenches 51 by an oxide layer 6 in a first active region RA1; an anode electrode covered in each of second trenches 52 by the oxide layer 6 in a second active region RA2; a P-type channel layer 2 formed in a surface layer of an N - -type semiconductor substrate 1; and an N + -Type layer 4 formed in a surface layer of the P-type channel layer 2 in the first active region RA1. An area of ​​the first active region RA1 is 20% or more and 80% or less of a sum of the area of ​​the first active region RA1 and an area of ​​the second active region RA2.

The application provides an image sensor with improved pixel field effect transistor GIDL and a preparation method. The image sensor comprises a pixel field effect transistor and a peripheral logic field effect transistor. The pixel field effect transistor comprises a charge transport gate and a floating diffusion active region. A gate edge region near one end of the floating diffusion active region in the charge transport gate has a different structure from a gate edge region of the peripheral logic field effect transistor. The electric field intensity of the gate edge region near one end of the floating diffusion active region in the charge transport gate is lower than that of a gate center region of the charge transport gate. The GIDL phenomenon of the pixel field effect transistor is improved, and the image quality of the CIS is improved.

Disclosed is a gated diode-based true random number generator capable of encrypting information. More particularly, a gated diode-based true random number generator according to an embodiment of the present disclosure includes a gated diode where a p+-i-n+ diode structure is positioned between a drain terminal and a source terminal, a gate-insulating film is positioned on an intrinsic region of the p+-i-n+ diode structure, and two gate terminals are positioned on the gate-insulating film; and a control transistor where a control drain terminal is connected to the source terminal, wherein the control gate terminal and the control source terminal are constituted together with the control drain terminal, and the control transistor controls electron injection into the p+-i-n+ diode structure according to control of a gate voltage VMOS applied through the control gate terminal.