18results about "Logic circuits using semiconductor devices" patented technology

A control device (100) for controlling a number N, with N ≥ 1, of actuators (200) for actuating N optical elements (310) of an optical system (300), comprising a control node (K2) coupling to the actuator (200) for providing a control voltage (V2) for the actuator (200), and an amplifier (110) configured to receive a supply voltage (V1) provided at an input node (K1) and to provide an output voltage (V3) at an output node (K3), wherein the amplifier (110) comprises a plurality M, with M ≥ 2, of current sources (111, 112) comprising at least one controlled current source (112) and a holding capacitor (113) for maintaining the level of the provided output voltage (V3), wherein the controlled current source (112) comprises a transistor (114), whose gate terminal can be controlled by an adjustable first control signal (S1),and has an adjustable resistor (115) coupled to the transistor (114).

The invention relates to a linearity detection system for an input buffer, and the system comprises a main buffer, a terminating resistor unit, an auxiliary buffer, a switched capacitor unit, an observation comparator, and a judgment unit. The input end of the main buffer and the first input end of the terminating resistor unit receive input signals respectively; the second input end of the terminating resistor unit is connected to a first common-mode voltage, the output end of the terminating resistor unit is connected to the input end of the auxiliary buffer, and the output end of the auxiliary buffer and the output end of the main buffer are connected to the input end of the observation comparator through the switched capacitor unit. The output end of the observation comparator is connected to the input end of the judgment unit, and the output end of the judgment unit is connected to the output end of the main buffer; the determination unit is used for determining a determination result for the main buffer and determining a compensation mode. The current linearity state of the main buffer can be rapidly detected in real time and a corresponding compensation mode can be obtained on the premise that a main signal chain is not interfered.

Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

To provide a semiconductor device which is formed using transistors having the same conductivity type, in which a steady current does not flow, and which can express a high level or a low level using a high power supply potential and a low power supply potential.SOLUTION: The semiconductor device includes a plurality of single-polarity transistors, a capacitor, first and second input terminals, and an output terminal. A signal whose logic is inverted from that of a signal input to the first input terminal is input to the second input terminal. In a circuit configuration called bootstrap in which two transistors having the same conductivity type are connected in series between a high power supply potential and a low power supply potential and a capacitor is provided between an output terminal and a gate of one of the transistors, secure bootstrap can be performed by generating a delay between signals output from the gate of the transistor and the output terminal.SELECTED DRAWING: Figure 3

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

This application provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided in this application can add 1 to and subtract 1 from an input logical value. On the basis of the ternary logic gate circuit, the ternary logic gate circuit is applied to a ternary logic circuit by using 27 single-variable functions of three-valued logic, so that a structure of the ternary logic circuit can be simplified, a quantity of transistors in the ternary logic circuit can be reduced, power consumption of the ternary logic circuit can be reduced, and computing efficiency of the ternary logic circuit can be improved.

A semiconductor device includes a first regulator, a logic circuit, and a first transmission circuit. The first regulator generates a first internal voltage. The logic circuit operates using the first internal voltage, and determines an operation mode. The first transmission circuit transmits, using the first internal voltage, an exit command of the first operation mode externally input as a first control signal during the first operation mode to the logic circuit as an internal exit command.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

A semiconductor device includes at least three arms. Channels of the first and second arms extend to a channel of the third arm. A ballistic electron current is generated from the channels of the first and second arms to the channel of the third arm when a current from the first arm flows to the second arm due to an application of a first voltage. A fin structure is located in the third arm and includes a gate above the fin structure. The gate is controlled using a second voltage. The fin structure is formed to induce an energy field structure that is shifted by an amount of the second voltage to control an opening through which the ballistic electron current of the gate passes, thereby subjecting the ballistic electrons to diffraction and then interference, which in turn changes a depletion width.

A driving device includes: for example, a supply circuit configured to generate a supply voltage; a driving circuit configured to generate a driving signal for a switching device by being supplied with the supply voltage; and a logic circuit configured to control the driving circuit according to a first input signal and a second input signal. The supply circuit sets the supply voltage to a first voltage value in a first mode and sets the supply voltage to one of a second voltage value that is less than the first voltage value and the first voltage value in a second mode. The logic circuit enables the second input signal in the first mode and disables the second input signal in the second mode.

The invention provides a phase inverter, a gate driving device and a display panel, and belongs to the technical field of display driving. The inverter includes an inversion control circuit, a first transistor, and a second transistor. The anti-phase control circuit is used for accessing a first anti-phase signal and outputting an anti-phase control signal; the first transistor comprises a control electrode which is connected with the anti-phase control circuit and is used for accessing an anti-phase control signal, a first electrode which is connected with a first voltage source, and a second electrode which is connected with the second transistor and the second anti-phase connecting end; the second transistor comprises a control electrode for accessing a first inverted signal, a first electrode connected with the first transistor and the second inverted connecting end, and a second electrode connected with a second voltage source and used for outputting a second inverted signal; wherein the breakdown voltage threshold of the first transistor is greater than that of the second transistor. Therefore, the voltage withstanding degree of the first transistor can be improved, the first transistor is not prone to breakdown failure, and the stability of the inverter is improved.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.

The purpose of the present disclosure is to provide a technique capable of suppressing malfunction of a power semiconductor element. The semiconductor element driving circuit includes: a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected; a first off semiconductor element that reduces a voltage of the first output terminal when turned on; a second off semiconductor element that reduces the voltage of the second output terminal when turned on; and an OFF control circuit that turns on the first OFF semiconductor element and the second OFF semiconductor element via the OFF pre-stage circuit.

To control a discharge current flowing during active discharge.SOLUTION: The drive device 400 includes a power source circuit 410 that generates a power source voltage VCC2, a drive circuit 420 that receives the supply of the power source voltage VCC2 and generates drive signals (GH, GL) of the switch elements (2Hu, 2Lu), and a logical circuit 430 that controls the drive circuit 420 according to a first signal INA and a second signal INB. The power source circuit 410 sets the power source voltage VCC2 to a first voltage V31 in the first mode, and sets the power source voltage VCC2 to a second voltage V31 lower than the first voltage V32 or the first voltage V31 in the second mode. The logic circuit 430 enables the second input signal INB in the first mode, and disables the second input signal INB in the second mode.SELECTED DRAWING: Figure 12

A power tool comprising a power source, a motor, a bridge circuit connected to the motor, a gate driver connected to the bridge circuit, and a control unit connected to the gate driver, configured to supply a three-state control signal to the gate driver. The gate driver is configured to control the bridge circuit to drive the motor based on the three-state control signal.

The invention provides a semiconductor device and an operation method of the semiconductor device. The semiconductor device includes a first regulator, a logic circuit, and a first transmission circuit. The first regulator generates a first internal voltage. The logic circuit operates using a first internal voltage and determines an operation mode. The first transmission circuit transmits an exit command of a first operation mode as an internal exit command to the logic circuit using a first internal voltage during the first operation mode, the exit command being externally input as a first control signal.

Various embodiments relate to an amplitude shift keying (ASK) demodulator for demodulating an input signal, comprising: a frequency filter configured to receive the input signal, wherein the frequency filter comprises an adjustable component configured to adjust a frequency response of the frequency filter; a rectifier configured to rectify an output of the frequency filter, wherein the rectifier comprises an adjustable current source configured to adjust a current consumption of the rectifier; a reference signal generator configured to generate a reference signal; a current-to-voltage converter configured to convert a current of the rectified signal into a rectified voltage and to convert a current of the reference signal into a reference voltage; and a comparator configured to compare the rectified voltage to the reference voltage and to generate a demodulated output signal.