71results about "Logic circuits using semiconductor devices" patented technology

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

The present application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit includes: a first transistor and a second transistor, the potential of the substrate end of the first transistor changes with the change of a first parameter, the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process of the potential generating circuit, and the potential of the substrate end of the second transistor changes with the change of the first parameter. Among them, the gate end of the first transistor is connected to the drain end of the first transistor, the substrate end of the first transistor serves as the first output end of the potential generating circuit, the gate end of the second transistor is connected to the drain end of the second transistor, and the substrate end of the second transistor serves as the second output end of the potential generating circuit. Thus, the first output end and the second output end can respectively output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

A control device (100) for controlling a number N, with N ≥ 1, of actuators (200) for actuating N optical elements (310) of an optical system (300), comprising a control node (K2) coupling to the actuator (200) for providing a control voltage (V2) for the actuator (200), and an amplifier (110) configured to receive a supply voltage (V1) provided at an input node (K1) and to provide an output voltage (V3) at an output node (K3), wherein the amplifier (110) comprises a plurality M, with M ≥ 2, of current sources (111, 112) comprising at least one controlled current source (112) and a holding capacitor (113) for maintaining the level of the provided output voltage (V3), wherein the controlled current source (112) comprises a transistor (114), whose gate terminal can be controlled by an adjustable first control signal (S1),and has an adjustable resistor (115) coupled to the transistor (114).

A method includes, during a time period A, in a computer storage element having first and second power inputs separated by an array of transistors, the computer storage element configured to store computer data bits, move an input of the array of transistors, a logic value "1" or "0" to a master latch; during a time period B, recovering at least a portion of the energy containing the input using the first clock; during a time period C, moving the input in the main latch to the isolation stage; recovering at least a portion of the energy containing the input from the isolation stage using a second clock during a time period D; during a time period E, recovering at least a portion of the energy containing the input from the slave latch using a third clock; and moving at least a portion of the input from the isolation stage to the slave latch during the time period F.

The invention relates to a linearity detection system for an input buffer, and the system comprises a main buffer, a terminating resistor unit, an auxiliary buffer, a switched capacitor unit, an observation comparator, and a judgment unit. The input end of the main buffer and the first input end of the terminating resistor unit receive input signals respectively; the second input end of the terminating resistor unit is connected to a first common-mode voltage, the output end of the terminating resistor unit is connected to the input end of the auxiliary buffer, and the output end of the auxiliary buffer and the output end of the main buffer are connected to the input end of the observation comparator through the switched capacitor unit. The output end of the observation comparator is connected to the input end of the judgment unit, and the output end of the judgment unit is connected to the output end of the main buffer; the determination unit is used for determining a determination result for the main buffer and determining a compensation mode. The current linearity state of the main buffer can be rapidly detected in real time and a corresponding compensation mode can be obtained on the premise that a main signal chain is not interfered.

A logic gate comprising a semiconductor device is provided. The semiconductor device includes a charge reservoir layer disposed between a first charge receiving layer and a second charge receiving layer. The first charge receiving layer defines a first current flow path connected at one end to a common output contact and at the other end to a drive contact. The second charge receiving layer defines a current flow path connected at one end to the common output contact and at the other end to a ground contact. The charge reservoir layer comprises a potential well having the lowest energy state of mobile charge carriers, which is at an energy lower than the lowest energy state of the mobile charge carriers of both the first and second charge receiving layers. The logic gate further comprises a control gate and a ground electrode separated from the charge receiving layers by a non-conductive layer. The control gate and the ground electrode are configured to apply input voltages to both ends of the semiconductor device such that mobile charge carriers confined within the charge reservoir layer move to the first charge receiving layer at a first applied input voltage and to the second charge receiving layer at a second applied input voltage.

Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

A logic gate including a semiconductor device is provided. The semiconductor device includes a charge reservoir disposed between a first charge-accepting layer and a second charge-accepting layer. The first charge accepting layer defines a first current flow path connected at one end to the common output contact and at the other end to the drive contact. The second charge accepting layer defines a current flow path connected at one end to the common output contact and at the other end to the ground contact. The charge repository includes a potential well having a lowest energy state of mobile charge carriers at an energy lower than that of the lowest energy state of mobile charge carriers of both the first and second charge accepting layers. The logic gate further includes a control gate and a ground electrode separated from the charge accepting layer by a non-conductive layer. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device such that mobile charge carriers confined within the charge repository are transferred to the first charge accepting layer at a first applied input voltage and to the second charge accepting layer at a second applied input voltage.

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

Provided is a reconfigurable logic device using an electrochemical potential. The reconfigurable logic device includes a first semiconductor channel and a second semiconductor channel, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculating a difference value corresponding to a difference between a first determination value determined with each different value according to whether the effective magnetic field direction of the first semiconductor channel is equal to the magnetization direction of the first ferromagnetic gate and a second determination value determined with each different value according to whether the effective magnetic field direction of the second semiconductor channel is equal to the magnetization direction of the second ferromagnetic gate, and compare the difference value with a reference value to determine an output value.

The invention relates to a chip system, a startup and shutdown manager, a power supply circuit and electronic equipment, and relates to the technical field of terminals. The chip system comprises a startup and shutdown manager, a power supply circuit and a data processing system, wherein the startup and shutdown manager comprises a digital logic circuit. The digital logic circuit is used for responding to the input of the device button and sending a first pulse signal to the power supply circuit through the enabling output end, and the first pulse signal is used for controlling the power supply circuit to supply power to the data processing system. In response to a constant electric signal received by the feedback controlled end from the feedback output end of the power supply circuit or the feedback output end of the data processing system, a first power supply signal is sent to the power supply circuit through the enabling output end, and the first power supply signal is used for controlling the power supply circuit to continuously supply power to the data processing system. Therefore, the cost can be reduced.

The utility model provides a drive circuit and a vehicle-mounted device, the vehicle-mounted device comprises a power supply, a load circuit and a drive circuit, the drive circuit comprises a comparator circuit, the comparator circuit is used for generating PWM waveform; the input end of the bootstrap circuit is connected with the output end of the comparator circuit, and the bootstrap circuit is used for charging according to the PWM waveform output by the comparator circuit and outputting a high-voltage signal; the control end of the transistor is connected with the output end of the bootstrap circuit, the first connecting end of the transistor is used for being connected with a power supply, the second connecting end of the transistor is used for being connected with a load circuit, and the transistor is used for conducting the first connecting end and the second connecting end according to a high-voltage signal output by the bootstrap circuit. According to the driving circuit, on the basis of ensuring power supply to the load circuit, more compact design layout can be realized, dependence on an integrated circuit (IC) can be eliminated, and the cost is reduced.

To provide a semiconductor device which is formed using transistors having the same conductivity type, in which a steady current does not flow, and which can express a high level or a low level using a high power supply potential and a low power supply potential.SOLUTION: The semiconductor device includes a plurality of single-polarity transistors, a capacitor, first and second input terminals, and an output terminal. A signal whose logic is inverted from that of a signal input to the first input terminal is input to the second input terminal. In a circuit configuration called bootstrap in which two transistors having the same conductivity type are connected in series between a high power supply potential and a low power supply potential and a capacitor is provided between an output terminal and a gate of one of the transistors, secure bootstrap can be performed by generating a delay between signals output from the gate of the transistor and the output terminal.SELECTED DRAWING: Figure 3

To solve a problem regarding driving control for a switch element in a signal transmission device.SOLUTION: In a first configuration, a signal transmission device 200X includes a transmission circuit 410, a receiving circuit 420 for outputting a driving control signal Ga, and an isolation circuit 430. The transmission circuit 410 drives at least either a first internal signal S1 or a second internal signal S2 at a specific period according to an external signal ACD. The receiving circuit 420 includes a detection circuit 455 capable of detecting that at least the period of the first internal signal S1 or the second internal signal S2 is the specific period, a first driving circuit 426 configured to make the gate of a switch element SW1 a high-impedance state according to the detection result of the detection circuit 455, and a second driving circuit 502 configured to turn on the switch element SW1 by inputting a specific voltage Gb to its gate according to the detection result, the specific voltage Gb has a voltage value of an on threshold value voltage of the switch element SW1 or more.SELECTED DRAWING: Figure 11

The present invention provides a memristor-based storage and computing integrated computing unit, an array circuit, and a control method. The drain of a first MOS tube of the computing unit is connected to a first voltage input signal, and the source of a second MOS tube is connected to a second voltage input signal; the gate of the first MOS tube and the gate of the second MOS tube are commonly connected to a control voltage signal; the source of the first MOS tube is connected to one end of the first memristor, and the drain of the second MOS tube is connected to one end of the second memristor; the other end of the first memristor and the other end of the second memristor are commonly connected to the gate of a fourth MOS tube; the drain of the fourth MOS tube is connected to the source of the third MOS tube, the source of the fourth MOS tube is connected to the drain of a fifth MOS tube, the source of the fifth MOS tube is grounded, and the drain of the third MOS tube serves as a current output end, thereby improving the accuracy of the circuit output current and realizing a neural network pruning function in hardware.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

This application provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided in this application can add 1 to and subtract 1 from an input logical value. On the basis of the ternary logic gate circuit, the ternary logic gate circuit is applied to a ternary logic circuit by using 27 single-variable functions of three-valued logic, so that a structure of the ternary logic circuit can be simplified, a quantity of transistors in the ternary logic circuit can be reduced, power consumption of the ternary logic circuit can be reduced, and computing efficiency of the ternary logic circuit can be improved.

A semiconductor device includes a first regulator, a logic circuit, and a first transmission circuit. The first regulator generates a first internal voltage. The logic circuit operates using the first internal voltage, and determines an operation mode. The first transmission circuit transmits, using the first internal voltage, an exit command of the first operation mode externally input as a first control signal during the first operation mode to the logic circuit as an internal exit command.

A push-pull dynamic amplifier is operable in a reset phase and an amplification phase. The amplifier includes a first NMOS input transistor and a first PMOS input transistor electrically coupled to a first input terminal and a first output terminal. A second NMOS input transistor and a second PMOS input transistor are electrically coupled to a second input terminal and a second output terminal. A first reset switch and a second reset switch are electrically coupled to the first output terminal and the second output terminal, respectively. A power switch is electrically coupled to the first PMOS transistor and the second PMOS transistor, and a ground switch is electrically coupled to the first NMOS transistor and the second NMOS transistor. During the reset phase, the reset switch is closed, and the power switch and the ground switch are open. During the amplification phase, the reset switch is open, and the power switch and the ground switch are closed.

The present disclosure relates to an inverter circuit. An inverter includes a semiconductor substrate. 2 The FET switch is disposed at the first surface of the semiconductor substrate, and the further switch is disposed at the first surface of the semiconductor substrate. 2 The FET switch has a current path coupled between a first reference terminal and a second reference terminal.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting layer defines a first current flow path that is connected to a common output contact at one end and a drive contact at the other end. The second charge accepting layer defines a current flow path that is connected to the common output contact at one end and a ground contact at the other end. The charge reservoir layer comprises a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers. The logic gate further comprises a control gate and a ground electrode that are separated from the charge accepting layers by non-conducting layers. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer are transferred to the first charge accepting layer at a first applied input voltage and transferred to the second charge accepting layer at a second applied input voltage.

A semiconductor device includes at least three arms. Channels of the first and second arms extend to a channel of the third arm. A ballistic electron current is generated from the channels of the first and second arms to the channel of the third arm when a current from the first arm flows to the second arm due to an application of a first voltage. A fin structure is located in the third arm and includes a gate above the fin structure. The gate is controlled using a second voltage. The fin structure is formed to induce an energy field structure that is shifted by an amount of the second voltage to control an opening through which the ballistic electron current of the gate passes, thereby subjecting the ballistic electrons to diffraction and then interference, which in turn changes a depletion width.

The present invention relates to a logic device (10) comprising: - a first and a second arm (12) through which a charging current passes; - a channel (16) that connects the arms (12, 14) and comprises a first zone of contact with the first arm (12) and a second zone of contact with the second arm (14), the arms (12, 14) and the channel (16) being able, in the first zone of contact, to convert a charging current into a spin current and, in the second zone of contact, to convert a spin current into a charging current; and - a unit (20) for controlling the direction of the charging current in the second arm (14), the control unit (20) comprising a sub-unit (22) for electrical control of a conversion.

To provide a semiconductor device which is configured using unipolar transistors, does not allow a steady current to flow, and can represent a high level or a low level using a high power supply potential and a low power supply potential.SOLUTION: A semiconductor device includes multiple unipolar transistors, a capacitive element, first and second input terminals, and an output terminal, and a signal whose logic is inverted from that of the signal input to the first input terminal is input to the second input terminal. This circuit configuration is called bootstrap, in which two unipolar transistors are connected in series between a high power supply potential and a low power supply potential, and a capacitance is provided between the output terminal and the gate of one of the transistors, and reliable bootstrap can be performed by generating a delay in the signal output from the gate of the transistor and the output terminal.SELECTED DRAWING: Figure 3

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.