36results about "Logic circuits using semiconductor devices" patented technology

The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

A control device (100) for controlling a number N, with N ≥ 1, of actuators (200) for actuating N optical elements (310) of an optical system (300), comprising a control node (K2) coupling to the actuator (200) for providing a control voltage (V2) for the actuator (200), and an amplifier (110) configured to receive a supply voltage (V1) provided at an input node (K1) and to provide an output voltage (V3) at an output node (K3), wherein the amplifier (110) comprises a plurality M, with M ≥ 2, of current sources (111, 112) comprising at least one controlled current source (112) and a holding capacitor (113) for maintaining the level of the provided output voltage (V3), wherein the controlled current source (112) comprises a transistor (114), whose gate terminal can be controlled by an adjustable first control signal (S1),and has an adjustable resistor (115) coupled to the transistor (114).

The invention relates to a linearity detection system for an input buffer, and the system comprises a main buffer, a terminating resistor unit, an auxiliary buffer, a switched capacitor unit, an observation comparator, and a judgment unit. The input end of the main buffer and the first input end of the terminating resistor unit receive input signals respectively; the second input end of the terminating resistor unit is connected to a first common-mode voltage, the output end of the terminating resistor unit is connected to the input end of the auxiliary buffer, and the output end of the auxiliary buffer and the output end of the main buffer are connected to the input end of the observation comparator through the switched capacitor unit. The output end of the observation comparator is connected to the input end of the judgment unit, and the output end of the judgment unit is connected to the output end of the main buffer; the determination unit is used for determining a determination result for the main buffer and determining a compensation mode. The current linearity state of the main buffer can be rapidly detected in real time and a corresponding compensation mode can be obtained on the premise that a main signal chain is not interfered.

Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

The invention relates to a chip system, a startup and shutdown manager, a power supply circuit and electronic equipment, and relates to the technical field of terminals. The chip system comprises a startup and shutdown manager, a power supply circuit and a data processing system, wherein the startup and shutdown manager comprises a digital logic circuit. The digital logic circuit is used for responding to the input of the device button and sending a first pulse signal to the power supply circuit through the enabling output end, and the first pulse signal is used for controlling the power supply circuit to supply power to the data processing system. In response to a constant electric signal received by the feedback controlled end from the feedback output end of the power supply circuit or the feedback output end of the data processing system, a first power supply signal is sent to the power supply circuit through the enabling output end, and the first power supply signal is used for controlling the power supply circuit to continuously supply power to the data processing system. Therefore, the cost can be reduced.

The utility model provides a drive circuit and a vehicle-mounted device, the vehicle-mounted device comprises a power supply, a load circuit and a drive circuit, the drive circuit comprises a comparator circuit, the comparator circuit is used for generating PWM waveform; the input end of the bootstrap circuit is connected with the output end of the comparator circuit, and the bootstrap circuit is used for charging according to the PWM waveform output by the comparator circuit and outputting a high-voltage signal; the control end of the transistor is connected with the output end of the bootstrap circuit, the first connecting end of the transistor is used for being connected with a power supply, the second connecting end of the transistor is used for being connected with a load circuit, and the transistor is used for conducting the first connecting end and the second connecting end according to a high-voltage signal output by the bootstrap circuit. According to the driving circuit, on the basis of ensuring power supply to the load circuit, more compact design layout can be realized, dependence on an integrated circuit (IC) can be eliminated, and the cost is reduced.

To provide a semiconductor device which is formed using transistors having the same conductivity type, in which a steady current does not flow, and which can express a high level or a low level using a high power supply potential and a low power supply potential.SOLUTION: The semiconductor device includes a plurality of single-polarity transistors, a capacitor, first and second input terminals, and an output terminal. A signal whose logic is inverted from that of a signal input to the first input terminal is input to the second input terminal. In a circuit configuration called bootstrap in which two transistors having the same conductivity type are connected in series between a high power supply potential and a low power supply potential and a capacitor is provided between an output terminal and a gate of one of the transistors, secure bootstrap can be performed by generating a delay between signals output from the gate of the transistor and the output terminal.SELECTED DRAWING: Figure 3

To solve a problem regarding driving control for a switch element in a signal transmission device.SOLUTION: In a first configuration, a signal transmission device 200X includes a transmission circuit 410, a receiving circuit 420 for outputting a driving control signal Ga, and an isolation circuit 430. The transmission circuit 410 drives at least either a first internal signal S1 or a second internal signal S2 at a specific period according to an external signal ACD. The receiving circuit 420 includes a detection circuit 455 capable of detecting that at least the period of the first internal signal S1 or the second internal signal S2 is the specific period, a first driving circuit 426 configured to make the gate of a switch element SW1 a high-impedance state according to the detection result of the detection circuit 455, and a second driving circuit 502 configured to turn on the switch element SW1 by inputting a specific voltage Gb to its gate according to the detection result, the specific voltage Gb has a voltage value of an on threshold value voltage of the switch element SW1 or more.SELECTED DRAWING: Figure 11

The present invention provides a memristor-based storage and computing integrated computing unit, an array circuit, and a control method. The drain of a first MOS tube of the computing unit is connected to a first voltage input signal, and the source of a second MOS tube is connected to a second voltage input signal; the gate of the first MOS tube and the gate of the second MOS tube are commonly connected to a control voltage signal; the source of the first MOS tube is connected to one end of the first memristor, and the drain of the second MOS tube is connected to one end of the second memristor; the other end of the first memristor and the other end of the second memristor are commonly connected to the gate of a fourth MOS tube; the drain of the fourth MOS tube is connected to the source of the third MOS tube, the source of the fourth MOS tube is connected to the drain of a fifth MOS tube, the source of the fifth MOS tube is grounded, and the drain of the third MOS tube serves as a current output end, thereby improving the accuracy of the circuit output current and realizing a neural network pruning function in hardware.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

This application provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided in this application can add 1 to and subtract 1 from an input logical value. On the basis of the ternary logic gate circuit, the ternary logic gate circuit is applied to a ternary logic circuit by using 27 single-variable functions of three-valued logic, so that a structure of the ternary logic circuit can be simplified, a quantity of transistors in the ternary logic circuit can be reduced, power consumption of the ternary logic circuit can be reduced, and computing efficiency of the ternary logic circuit can be improved.

A semiconductor device includes a first regulator, a logic circuit, and a first transmission circuit. The first regulator generates a first internal voltage. The logic circuit operates using the first internal voltage, and determines an operation mode. The first transmission circuit transmits, using the first internal voltage, an exit command of the first operation mode externally input as a first control signal during the first operation mode to the logic circuit as an internal exit command.

A push-pull dynamic amplifier is operable in a reset phase and an amplification phase. The amplifier includes a first NMOS input transistor and a first PMOS input transistor electrically coupled to a first input terminal and a first output terminal. A second NMOS input transistor and a second PMOS input transistor are electrically coupled to a second input terminal and a second output terminal. A first reset switch and a second reset switch are electrically coupled to the first output terminal and the second output terminal, respectively. A power switch is electrically coupled to the first PMOS transistor and the second PMOS transistor, and a ground switch is electrically coupled to the first NMOS transistor and the second NMOS transistor. During the reset phase, the reset switch is closed, and the power switch and the ground switch are open. During the amplification phase, the reset switch is open, and the power switch and the ground switch are closed.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

A semiconductor device includes at least three arms. Channels of the first and second arms extend to a channel of the third arm. A ballistic electron current is generated from the channels of the first and second arms to the channel of the third arm when a current from the first arm flows to the second arm due to an application of a first voltage. A fin structure is located in the third arm and includes a gate above the fin structure. The gate is controlled using a second voltage. The fin structure is formed to induce an energy field structure that is shifted by an amount of the second voltage to control an opening through which the ballistic electron current of the gate passes, thereby subjecting the ballistic electrons to diffraction and then interference, which in turn changes a depletion width.

A level shifter includes a current output amplifier configured to output a first output current and a second output current through first and second output terminals thereof, respectively, a first resistor configured to be connected between each of an inverted input terminal and the first output terminal of the current output amplifier and an application terminal of a ground potential, and a second resistor configured to be connected between the second output terminal of the current output amplifier and an application terminal of a negative potential lower than the ground potential. A first analog signal referenced to the ground potential is accepted at a non-inverted input terminal of the current output amplifier, and a second analog signal referenced to the negative potential is outputted through one terminal of the second resistor.

This invention relates to an amplifier for converting a differential input signal into a single-ended output signal. Specifically, this invention relates to an amplifier with a reduced inherent time constant of the conversion. The invention provides an amplifier including a conversion circuit for converting a differential input signal into a single-ended output signal. The conversion circuit includes: an input section for receiving the differential input signal; and an output section including an output port for providing the single-ended output signal, wherein the output section includes a capacitor element for reducing the inherent time constant of the conversion circuit.

There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting layer defines a first current flow path that is connected to a common output contact at one end and a drive contact at the other end. The second charge accepting layer defines a current flow path that is connected to the common output contact at one end and a ground contact at the other end. The charge reservoir layer comprises a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers. The logic gate further comprises a control gate and a ground electrode that are separated from the charge accepting layers by non-conducting layers. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer are transferred to the first charge accepting layer at a first applied input voltage and transferred to the second charge accepting layer at a second applied input voltage.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

A driving device includes: for example, a supply circuit configured to generate a supply voltage; a driving circuit configured to generate a driving signal for a switching device by being supplied with the supply voltage; and a logic circuit configured to control the driving circuit according to a first input signal and a second input signal. The supply circuit sets the supply voltage to a first voltage value in a first mode and sets the supply voltage to one of a second voltage value that is less than the first voltage value and the first voltage value in a second mode. The logic circuit enables the second input signal in the first mode and disables the second input signal in the second mode.

The invention discloses a drain electrode ESD protection circuit capable of being used for a GaN power integrated circuit. The drain electrode ESD protection circuit comprises a main protection device used for discharging an ESD circuit, a two-stage driving circuit used for driving the main protection device in an ESD event and a source follower connected with the two-stage driving circuit. The first-stage driving circuit is used for driving the source follower, so that the second-stage driving circuit can pre-charge the grid electrode of the main protection device, and the grid electrode driving voltage of the main protection device is further improved. While the output voltage of the first-stage driving circuit is improved, the boost of the second-stage driving circuit can be controlled in a safe range and is more stable. The bootstrap voltage of the second-stage driving circuit can be more completely output to the grid electrode of the main protection device due to the increase of the voltage of the first-stage driving circuit. Therefore, the main protection device can be opened more quickly in an ESD event, larger ESD current can be discharged, and the ESD protection circuit can be used for solving the problems of early closing, temperature drift and the like of the ESD protection circuit.

The invention relates to a self-adaptive multi-stage gate drive circuit for a silicon carbide power device, and the core idea of the circuit is that a single switching process (switching on or switching off) is decomposed into a plurality of key stages, and the optimal gate drive intensity (namely drive impedance) is matched for each stage. The circuit comprises a main driving unit for providing basic driving capability; the programmable gate impedance network consists of a plurality of resistor circuits which are connected in parallel and can be independently controlled by an electric switch (such as a small-signal MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)); the state monitoring unit is used for monitoring a physical quantity capable of reflecting a switching process in real time through a high-speed comparator or an ADC (Analog to Digital Converter), preferably gate-source voltage Vgs; and the digital control unit (such as an FPGA or a CPLD) is used as the core of the whole adaptive control. The invention also relates to a self-adaptive multistage gate driving method for driving the silicon carbide power device.

The invention provides a phase inverter, a gate driving device and a display panel, and belongs to the technical field of display driving. The inverter includes an inversion control circuit, a first transistor, and a second transistor. The anti-phase control circuit is used for accessing a first anti-phase signal and outputting an anti-phase control signal; the first transistor comprises a control electrode which is connected with the anti-phase control circuit and is used for accessing an anti-phase control signal, a first electrode which is connected with a first voltage source, and a second electrode which is connected with the second transistor and the second anti-phase connecting end; the second transistor comprises a control electrode for accessing a first inverted signal, a first electrode connected with the first transistor and the second inverted connecting end, and a second electrode connected with a second voltage source and used for outputting a second inverted signal; wherein the breakdown voltage threshold of the first transistor is greater than that of the second transistor. Therefore, the voltage withstanding degree of the first transistor can be improved, the first transistor is not prone to breakdown failure, and the stability of the inverter is improved.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.

An application specific integrated circuit (A SIC) can drive semiconductor devices, such as, radio frequency amplifiers, switches, etc. The A SIC can include a supply and reference voltage generation circuit, a digital core, a clock generator, a plurality of analog-to-digital converters, low and high-speed communications interfaces, drain and gate sensing circuits (that can include one or more current sense amplifiers), and a gate driver circuit. The ASIC can be a low voltage semiconductor integrated circuit.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

The purpose of the present disclosure is to provide a technique capable of suppressing malfunction of a power semiconductor element. The semiconductor element driving circuit includes: a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected; a first off semiconductor element that reduces a voltage of the first output terminal when turned on; a second off semiconductor element that reduces the voltage of the second output terminal when turned on; and an OFF control circuit that turns on the first OFF semiconductor element and the second OFF semiconductor element via the OFF pre-stage circuit.

To control a discharge current flowing during active discharge.SOLUTION: The drive device 400 includes a power source circuit 410 that generates a power source voltage VCC2, a drive circuit 420 that receives the supply of the power source voltage VCC2 and generates drive signals (GH, GL) of the switch elements (2Hu, 2Lu), and a logical circuit 430 that controls the drive circuit 420 according to a first signal INA and a second signal INB. The power source circuit 410 sets the power source voltage VCC2 to a first voltage V31 in the first mode, and sets the power source voltage VCC2 to a second voltage V31 lower than the first voltage V32 or the first voltage V31 in the second mode. The logic circuit 430 enables the second input signal INB in the first mode, and disables the second input signal INB in the second mode.SELECTED DRAWING: Figure 12

Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET. The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.