Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

a logic circuit and transistor technology, applied in logic circuits, digital storage, instruments, etc., can solve problems such as serious impedement and delay in the operation of a preceding logic circuit stag

Inactive Publication Date: 2001-11-15
NEC ELECTRONICS CORP
View PDF0 Cites 22 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, by increasing the gate width, the input capacitance viewed from the input signal is increased resulting in a delay in the operation of a preceding logic circuit stage (not shown).
Where a plurality of logic gate stages are present, it is necessary for the high speed operation of the cir...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same
  • Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same
  • Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0041] FIG. 2A is a circuit diagram showing the logic circuit according to the invention applied to a two-input NAND logic circuit having the BiCMOS structure. Comparing FIGS. 2A and 1, this embodiment of the invention is significantly different from the prior art NAND circuit in that the current paths for pulling down output stage BiP transistor base potential and pulling out charge from the load are constituted by independent n-channel MOS transistors M.sub.11 and M.sub.14, respectively, instead of the series n-channel MOS transistors M.sub.21 and M.sub.22 and the series n-channel MOS transistors M.sub.25 and M.sub.26 in the prior art.

[0042] In this embodiment, an input signal A is inputted to the gate of a p-channel MOS transistor M.sub.12 as well as the gate of the n-channel MOS transistor M.sub.11. The source of the p-channel MOS transistor M.sub.12 is connected to a high potential power supply line 3 (at V.sub.cc). A separate input signal B is inputted to the gate of a p-chann...

third embodiment

[0053] the invention will now be described with reference to FIG. 4. Referring to the figure, this embodiment is the same as the preceding embodiments in the point wherein the output X.sub.0 is pulled down by using a single n-channel MOS transistor M.sub.41. A feature of this embodiments resides in that the output X.sub.0 is pulled up by using only BiP transistors. The inverse signal .gradient.B which is inputted to the source of the n-channel MOS transistor M.sub.41, is also inputted to the base of the BiP transistor Q.sub.41, and the inverse signal .gradient.A inverse to the signal A is inputted to a base of a BiP transistor Q.sub.42 which is parallel with the transistor Q.sub.41.

[0054] In this embodiment, when the signal A and the inverse signal .gradient.B become "high" and "low", respectively (i.e., A=1, B=1), the n-channel MOS transistor M.sub.41 is turned on. At this time, the inverse signals .gradient.A and .gradient.B both become "low", and the two BiP transistors Q.sub.41 ...

fourth embodiment

[0056] the invention will now be described with reference to FIG. 6. This embodiment is a two-input NOR circuit having the BiCMOS structure. Referring to FIG. 6, the base potential on a BiP transistor Q.sub.6 is pulled down by parallel n-channel MOS transistors M.sub.62 and M.sub.63, to the gates of which input signals A and B are inputted. Transistors M.sub.64 and M.sub.65 are for pulling down an output X.sub.1. For the pull-up of the base potential on the BiP transistor Q.sub.6, a single p-channel MOS transistor M.sub.61 is provided, to the gate and source of which the signal A and the inverse signal .gradient.B are inputted, respectively. In the prior art NOR circuit, this part is constituted by two series p-channel MOS transistors. In such a case, there is a problem in that, when providing the "high" output, the current capacity of the p-channel MOS transistors in the "on" state thereof is low and unable to supply sufficient base current to the transistor Q.sub.6. In other words...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

A logic circuit performs a predetermined logic operation by supplying charge to an external load or putting out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area. Adjacent ones of the logic circuits have a common source diffusion layer so that the load capacitance with respect to the inverse signal can be significantly reduced, thus enabling the high speed operation.

Description

[0001] (1) Field of the Invention[0002] The present invention relates to logic circuits and semiconductor integrated circuits using the same, and more particularly to logic circuits which can be advantageously utilized in multiple input circuits, such as semiconductor memory decoder circuits, provided in an array form, and semiconductor integrated circuits using theame.[0003] (2) Description of the Related Art[0004] As an example of the prior art multiple input logic circuit, a two-input NAND circuit comprising a bipolar transistor and a MOS transistor (this structure being hereinafter referred to as BiCMOS structure) will now be described. FIG. 1 is ircuit diagram showing the NAND circuit. As shown, the NAND circuit comprises a logic circuit stage 1 having a CMOS transistor structure and an output stage 2 having bipolar / MOS transistor 710 structure. Specifically, the logic circuit stage 1 includes a parallel circit of two p-channel MOS transistors M.sub.23 and M.sub.24 and a series...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G11C11/40G11C11/413G11C11/408H03K19/017H03K19/08H03K19/0944H03K19/20
CPCH03K19/09448G11C11/40
Inventor TAKAHASHI, HIROYUKISATO, MITSURU
Owner NEC ELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap