Memory management unit with pre-filling capability

Abstract

Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) (206, 208) with address translation (202-204) entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices (214), or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns (216). Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

Description

[0001] Claim of priority under 35 U.S.C. §119

[0002] This patent application claims priority to Provisional Application No. 61 / 448,839, filed March 3, 2011, entitled "MEMORY MANAGEMENT UNIT WITH PRE-FILLING CAPABILITY," which states The provisional application is assigned to the present assignee and is hereby incorporated by reference herein. technical field

[0003] The disclosed embodiments are directed to a memory management unit (MMU) for managing the translation of memory addresses from virtual addresses to physical addresses. More particularly, exemplary embodiments are directed to efficient techniques, such as pre-population, for managing translation caches that can be used for virtual-to-physical address translations, such as pre-population. Background technique

[0004] Modern operating systems often use virtual addressing schemes in order to maximize the use of physical memory space in the processor. Virtual memory is well known in the art. Virtual memory is ...

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