Memory management unit with pre-filling capability

A pre-filled, single technology, used in memory systems, instruments, electrical digital data processing, etc., can solve problems such as increasing TLB and TLB degradation

Inactive Publication Date: 2013-12-11
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for streaming access, increasing the TLB size does not confer the same benefit
In fact, even though the theoretical TLB size increases towards infinity, in several cases it can be shown that TLB performance can be continuously and severely degraded by misses and accompanying pauses

Method used

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Embodiment Construction

[0032] Aspects of the invention are disclosed in the following description and associated drawings directed to specific embodiments of the invention. Alternative embodiments are conceivable without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0033] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the invention. As used...

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Abstract

Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) (206, 208) with address translation (202-204) entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices (214), or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns (216). Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

Description

[0001] Claim of priority under 35 U.S.C. §119 [0002] This patent application claims priority to Provisional Application No. 61 / 448,839, filed March 3, 2011, entitled "MEMORY MANAGEMENT UNIT WITH PRE-FILLING CAPABILITY," which states The provisional application is assigned to the present assignee and is hereby incorporated by reference herein. technical field [0003] The disclosed embodiments are directed to a memory management unit (MMU) for managing the translation of memory addresses from virtual addresses to physical addresses. More particularly, exemplary embodiments are directed to efficient techniques, such as pre-population, for managing translation caches that can be used for virtual-to-physical address translations, such as pre-population. Background technique [0004] Modern operating systems often use virtual addressing schemes in order to maximize the use of physical memory space in the processor. Virtual memory is well known in the art. Virtual memory is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/10
CPCG06F12/1027G06F2212/6026G06F2212/6028G06F2212/654G06F12/10
Inventor 博胡斯拉夫·雷赫利克托马斯·安德鲁·萨托里乌斯迈克尔·威廉·莫罗雷蒙德·P·帕尔马
Owner QUALCOMM INC
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